Z85233 Datasheet, PDF (172/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
The Z180™ Interfaced with the SCC at MHZ
Interrupt Condition
7
IP
Set
IEI High?
IUS
Set
CPU Read, Write, or Reset
INT
Active
Wait For CPU
/INTACK Cycle
/INTACK * IEI * /RD
IP
Cleared
IEO High?
IUS
Cleared
Return To Main Program
Figure 12. SCC Interrupt Status Diagram
The SCC uses /INTACK (Interrupt Acknowledge) for
recognition of an interrupt acknowledge cycle. This pin,
used with /RD, allows the SCC to gate its interrupt vector
onto the data bus. An active /RD signal during an interrupt
acknowledge cycle performs two functions. First, it allows
the highest priority device requesting an interrupt to place
its vector on the data bus. Secondly, it sets the IUS bit in
the highest priority device to show the device is now under
service.
UM010901-0601
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