Z85233 Datasheet, PDF (108/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

USER’S MANUAL
5
CHAPTER 5
REGISTER DESCRIPTIONS
5.1 INTRODUCTION
This section describes the functions of the various bits in
the registers of the SCC (Tables 5-1 and 5-2). Reserved
bits are not used in this implementation of the device and
may or may not be physically present in the device. For the
register addresses, also refer to Tables 2-1, 2-2 and 2-5 in
Chapter 2. Reserved bits that are physically present are
readable and writable but reserved bits that are not present
will always be read as zero. To ensure compatibility with fu-
ture versions of the device, reserved bits should always be
written with zeros. Reserved commands are not used for
the same reason.
.
Table 5-1. SCC Write Registers
Reg
WR0
WR1
WR2
Description
Reg. pointers, various initialization commands
Transmit and Receive interrupt enables,
WAIT/DMA commands
Interrupt Vector
WR3²
WR4²
WR5²
WR6
WR7
WR7'¹
WR8
WR9
Receive parameters and control modes
Transmit and Receive modes and parameters
Transmit parameters and control modes
Sync Character or SDLC address
Sync Character or SDLC flag
Extended Feature and FIFO Control
(WR7 Prime)
Transmit buffer
Master Interrupt control and reset commands
WR10^{2 Miscellaneous transmit and receive control bits}
WR11 Clock mode controls for receive and transmit
WR12 Lower byte of baud rate generator
WR13 Upper byte of baud rate generator
WR14 Miscellaneous control bits
WR15 External status interrupt enable control
Notes for Tables 5-1 and 5-2:
1. ESCC and 85C30 only.
2. On the ESCC and 85C30, these registers are readable as
RR9, RR4, RR5, and RR11, respectively, when WR7' D6=1.
Refer to the description of WR7 Prime for enabling the ex-
tended read capability.
3. This feature is not available on NMOS.
Table 5-2. SCC Read Registers
Reg
RR0
RR1
RR2
Description
Transmit and Receive buffer status and external
status
Special Receive Condition status
Modified interrupt vector (Channel B only),
Unmodified interrupt vector (Channel A only)
RR3
RR4²
RR5²
RR6³
Interrupt pending bits (Channel A only)
Transmit and Receive modes and parameters
(WR4)
Transmit parameters and control modes (WR5)
SDLC FIFO byte counter lower byte (only when
enabled)
RR7³
RR8
RR9²
RR10
SDLC FIFO byte count and status (only when
enabled)
Receive buffer
Receive parameters and control modes (WR3)
Miscellaneous status bits
RR11²
RR12
RR13
RR14²
RR15
Miscellaneous transmit and receive control bits
(WR10)
Lower byte of baud rate generator time constant
Upper byte of baud rate generator time constant
Extended Feature and FIFO Control (WR7
Prime)
External Status interrupt information
UM010901-0601
5-1