Z85233 Datasheet, PDF (133/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Register Descriptions
5.3 READ REGISTERS (Continued)
Read Register 7 *
D7 D6 D5 D4 D3 D2 D1 D0
BC8
BC9
BC10
BC11
BC12
BC13
FDA: FIFO Data Available
1 = Status Reads from FIFO
0 = Status Reads from ESCC
FOS: FIFO Overflow Status
1 = FIFO Overflowed
0 = Normal
* Can only be accessed if the SDLC FIFO enhancement
is enabled (WR15 bit D2 set to 1)
SDLC FIFO Status and Byte Count (MSB)
Figure 5-24. Read Register 7 (Not on NMOS)
5.3.11 Read Register 10
RR10 contains some miscellaneous status bits. Unused
bits are always 0. Bit positions for RR10 are shown in
Figure 5-25.
Read Register 10
D7 D6 D5 D4 D3 D2 D1 D0
0
On Loop
0
0
Loop Sending
0
Two Clocks Missing
One Clock Missing
Figure 5-25. Read Register 10
Table 5-13. .Read Register 7 FIFO Status Decoding
Bit D7
1
0
FIFO Data Available Status
Status reads come from FIFO
(FIFO is not Empty)
Status reads bypass FIFO
because FIFO is Empty)
Bit D6
1
0
FIFO Overflow Status
FIFO has overflowed
Normal operation
If the FIFO overflows, the FIFO and the FIFO Overflow
Status bit are cleared by disabling and then re-enabling the
FIFO through the FIFO control bit (WR15, D2). Otherwise,
this register returns an image of RR3.
On the NMOS version, a read to this location returns an
image of RR3.
5.3.9 Read Register 8
RR8 is the Receive Data register.
5.3.10 Read Register 9 (ESCC and 85C30
Only)
On the ESCC, Read Register 9 reflects the contents of
Write Register 3 provided the Extended Read option has
been enabled.
On the NMOS/CMOS version, a read to this location re-
turns an image of RR13.
Bit 7: One Clock Missing status
While operating in the FM mode, the DPLL sets this bit to
1 when it does not see a clock edge on the incoming lines
in the window where it expects one. This bit is latched until
reset by a Reset Missing Clock or Enter Search Mode
command in WR14. In the NRZI mode of operation and
while the DPLL is disabled, this bit is always 0.
Bit 6: Two Clocks Missing status
While operating in the FM mode, the DPLL sets this bit to
1 when it does not see a clock edge in two successive
tries. At the same time the DPLL enters the Search mode.
This bit is latched until reset by a Reset Missing Clock or
Enter Search Mode command in WR14, bit 5-7. In the
NRZI mode of operation and while the DPLL is disabled,
this bit is always 0.
Bit 4: Loop Sending status
This bit is set to 1 in SDLC Loop mode while the transmitter
is in control of the Loop, that is, while the SCC is actively
transmitting on the loop. This bit is reset at all other times.
This bit can be polled in SDLC mode to determine when
the closing flag has been sent.
Bit 1: On Loop status
This bit is set to 1 while the SCC is actually on loop in
SDLC Loop mode. This bit is set to 1 in the X21 mode
(Loop mode selected while in monosync) when the trans-
mitter goes active. This bit is 0 at all other times. This bit
can also be pulled in SDLC mode to determine when the
closing flag has been sent.
5-26
UM010901-0601