Z85233 Datasheet, PDF (68/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
SCC/ESCC Ancillary Support Circuitry
3.4 DPLL DIGITAL PHASE-LOCKED LOOP
Each channel of the SCC contains a digital phase-locked Figure 3-5 shows a block diagram of the digital phase-
3 ^{loop that can be used to recover clock information from a locked loop. It consists of a 5-bit counter, an edge detector,}
data stream with NRZI, FM, NRZ, or Manchester encod- and a pair of output decoders. The clock for the DPLL
ing. The DPLL is driven by a clock nominally at 32 (NRZI) comes from the output of a two-input multiplexer, and the
or 16 (FM) times the data rate. The DPLL uses this clock, two outputs go to the transmitter and receive clock
along with the data stream, to construct a receive clock for multiplexers. The DPLL is controlled by seven commands
the data. This clock can then be used as the SCC receive encoded in WR14 bits D7, D6 and D5.
clock, the transmit clock, or both.
RxD
Edge Detector
Count Modifier
Decode
Receive
Clock
5-Bit Counter
Decode
Transmit
Clock
Figure 3-5. Digital Phase-Locked Loop
The clock source for the DPLL is selected issuing one of
the two commands in WR14, that is:
WR14 (7-5) = 100 selects the BRG
WR14 (7-5) = 101 selects the /RTxC pin
The first command selects the baud rate generator as the
clock source. The other command selects the /RTxC pin
as the clock source, independent of whether the /RTxC pin
is a simple input or part of the crystal oscillator circuit.
Initialization of the DPLL is done at any time during the ini-
tialization sequence, but should be done after the clock
modes have been selected in WR11, and before the re-
ceiver and transmitter are enabled. When initializing the
DPLL, the clock source should be selected first, followed
by the selection of the operating mode.
To avoid metastable problems in the counter, the clock
source selection is made only while DPLL is disabled,
since arbitrarily narrow pulses are generated at the output
of the multiplexer when it changes status.
The DPLL is programmed to operate in one of two modes,
as selected by commands in WR14.
WR14 (7-5) = 111 selects NRZI mode
WR14 (7-5) = 110 selects FM mode
Note: A channel or hardware reset disables the DPLL, se-
lects the /RTxC pin as the clock source for the DPLL, and
places it in the NRZI mode.
As in the case of the clock source selection, the mode of
operation is only changed while the DPLL is disabled to
prevent unpredictable results.
In the NRZI mode, the DPLL clock must be 32 times the
data rate. In this mode, the transmit and receive clock out-
puts of the DPLL are identical, and the clocks are phased
so that the receiver samples the data in the middle of the
bit cell. In NRZI mode, the DPLL does not require a transi-
tion in every bit cell, so this mode is useful for recovering
the clocking information from NRZ and NRZI data streams.
In the FM mode, the DPLL clock must be 16 times the data
rate. In this mode, the transmit clock output of the DPLL
lags the receive clock outputs by 90 degrees to make the
transmit and receive bit cell boundaries the same, be-
cause the receiver must sample FM data at one-quarter
and three-quarters bit time.
The DPLL is enabled by issuing the Enter Search Mode
command in WR14; that is WR14 (7-5) = 001. The Enter
Search Mode command unlocks the counter, which is held
while the DPLL is disabled, and enables the edge detector.
If the DPLL is already enabled when this command is is-
sued, the DPLL also enters Search Mode.
3-7
UM010901-0601