Z85233 Datasheet, PDF (76/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

USER’S MANUAL
4
CHAPTER 4
DATA COMMUNICATION MODES
4.1 INTRODUCTION
The SCC provides two independent, full-duplex channels
programmable for use in any common asynchronous or
synchronous data communication protocol. The data com-
munication protocols handled by the SCC are:
s Asynchronous mode:
Asynchronous (x16, x32, or x64 clock
Isochronous (x1 clock)
s Character-Oriented mode:
Monosynchronous
Bisynchronous
External Synchronous
s Bit-Oriented mode
SDLC/HDLC
SDLC/HDLC Loop
4.1.1 Transmit Data Path Description
A diagram of the transmit data path is shown in Figure 4-1.
The transmitter has a Transmit Data buffer (a 4-byte deep
FIFO on the ESCC, a one byte deep buffer on the
NMOS/CMOS version) which is addressed through WR8.
It is not necessary to enable the transmit buffer. It is
available in all modes of operation. The Transmit Shift
register is loaded from either WR6, WR7, or the Transmit
Data buffer. In Synchronous modes, WR6 and WR7 are
programmed with the sync characters. In Monosync mode,
an 8-bit or 6-bit sync character is used (WR6), whereas a
16-bit sync character is used in the Bisynchronous mode
(WR6 and WR7). In bit-oriented Synchronous modes, the
SDLC flag character (7E hex) is programmed in WR7 and
is loaded into the Transmit Shift Register at the beginning
and end of each message.
Internal Data Bus
WR8
WR7
WR6
SYNC Register SYNC Register
20-Bit TX Shift Register
To Other Channel
TX Buffer (1-Byte; NMOS/CMOS)
TX FIFO (4 Byte; ESCC)
Internal TxD
Final TX
MUX
TxD
Zero
Insert
5-Bit Delay
CRC-SDLC
CRC-Gen
ASYNC
SYNC
SDLC
Transmit
MUX & 2-Bit
Delay
Transmit Clock
NRZI
Encode
From Receiver
Figure 4-1. Transmit Data Path
UM010901-0601
4-1