Z85233 Datasheet, PDF (32/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

A//B
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
PNT2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
PNT1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
PNT0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Table 2-5. Z85X30 Register Map
WRITE
WR0B
WR1B
WR2
WR3B
WR4B
WR5B
WR6B
WR7B
WR0A
WR1A
WR2
WR3A
WR4A
WR5A
WR6A
WR7A
Read 8530
85C30/230
WR15 D2 = 0
RR0B
RR1B
RR2B
RR3B
(RR0B)
(RR1B)
(RR2B)
(RR3B)
RR0A
RR1A
RR2A
RR3A
(RR0A)
(RR1A)
(RR2A)
(RR3A)
With Point High Command
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
WR8B
WR9
WR10B
WR11B
RR8B
(RR13B)
RR10B
(RR15B)
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
WR12B
WR13B
WR14B
WR15B
RR12B
RR13B
RR14B
RR15B
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
WR8A
WR9
WR10A
WR11A
RR8A
(RR13A)
RR10A
(RR15A)
1
1
0
0
1
1
0
1
1
1
1
0
WR12A
WR13A
WR14A
RR12A
RR13A
RR14A
1
1
1
1
WR15A
RR15A
Notes:
WR15 bit D2 enables status FIFO function. (Not available on NMOS)
WR7' bit D6 enables extend read function. (Only on ESCC and 85C30)
SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
85C30/230
WR15 D2=1
2
WR15 D2=1
WR7' D6=1
RR0B
RR1B
RR2B
RR3B
RR0B
RR1B
RR2B
RR3B
(RR0B)
(RR1B)
RR6B
RR7B
(WR4B)
(WR5B)
RR6B
RR7B
RR0A
RR1A
RR2A
RR3A
RR0A
RR1A
RR2A
RR3A
(RR0A)
(RR1A)
RR6A
RR7A
(WR4A)
(WR5A)
RR6A
RR7A
RR8B
(RR13B)
RR10B
(RR15B)
RR12B
RR13B
RR14B
RR15B
RR8A
(RR13A)
RR10A
(RR15A)
RR12A
RR13A
RR14A
RR15A
RR8B
(WR3B)
RR10B
(WR10B)
RR12B
RR13B
(WR7’B)
RR15B
RR8A
(WR3A)
RR10A
(WR10A)
RR12A
RR13A
(WR7’A)
RR15A
UM010901-0601
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