Z85233 Datasheet, PDF (126/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Register Descriptions
5.2.16 Write Register 13 (Upper Byte of Baud ^{source to the /RTxC pin and selects NRZI mode. The Enter}
Rate Generator Time Constant)
Search Mode command enables the DPLL after a reset.
WR13 contains the upper byte of the time constant for the
baud rate generator. Bit positions for WR13 are shown in
Null Command (000). This command has no effect on
the DPLL.
5
Figure 5-16.
Write Register 13
D7 D6 D5 D4 D3 D2 D1 D0
Enter Search Mode Command (001). Issuing this com-
mand causes the DPLL to enter the Search mode, where
the DPLL searches for a locking edge in the incoming data
stream. The action taken by the DPLL upon receipt of this
command depends on the operating mode of the DPLL.
TC8
TC9
TC10
TC11
TC12
TC13
TC14
TC15
Upper Byte of
Time Constant
Figure 5-16. Write Register 13
5.2.17 Write Register 14 (Miscellaneous Con-
trol Bits)
WR14 contains some miscellaneous control bits. Bit
positions for WR14 are shown in Figure 5-17. For DPLL
function, refer to section 3.4 as well.
Write Register 14
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 Null Command
0 0 1 Enter Search Mode
0 1 0 Reset Missing Clock
0 1 1 Disable DPLL
1 0 0 Set Source = BR Generator
1 0 1 Set Source = /RTxC
1 1 0 Set FM Mode
1 1 1 Set NRZI Mode
BR Generator Enable
BR Generator Source
/DTR/Request Function
Auto Echo
Local Loopback
In NRZI mode, the output of the DPLL is High while the
DPLL is waiting for an edge in the incoming data stream.
After the Search mode is entered, the first edge the DPLL
sees is assumed to be a valid data edge, and the DPLL be-
gins the clock recovery operation from that point. The
DPLL clock rate must be 32x the data rate in NRZI mode.
Upon leaving the Search mode, the first sampling edge of
the DPLL occurs 16 of these 32x clocks after the first data
edge, and the second sampling occurs 48 of these 32x
clocks after the first data edge. Beyond this point, the
DPLL begins normal operation, adjusting the output to re-
main in sync with the incoming data.
In FM mode, the output of the DPLL is Low while the DPLL
is waiting for an edge in the incoming data stream. The first
edge the DPLL detects is assumed to be a valid clock
edge. For this to be the case, the line must contain only
clock edges; i.e. with FM1 encoding, the line must be con-
tinuous 0s. With FM0 encoding the line must be continu-
ous 1s, whereas Manchester encoding requires alternat-
ing 1s and 0s on the line. The DPLL clock rate must be 16
times the data rate in FM mode. The DPLL output causes
the receiver to sample the data stream in the nominal cen-
ter of the two halves of the bit to decide whether the data
was a 1 or a 0.
After this command is issued, as in NRZI mode, the DPLL
starts sampling immediately after the first edge is detect-
ed. (In FM mode, the DPLL examines the clock edge of ev-
ery other bit to decide what correction must be made to re-
main in sync.) If the DPLL does not see an edge during the
expected window, the one clock missing bit in RR10 is set.
If the DPLL does not see an edge after two successive at-
tempts, the two clocks missing bits in RR10 are set and the
DPLL automatically enters the Search mode. This com-
mand resets both clocks missing latches.
Figure 5-17. Write Register 14
Bits D7-D5: Digital Phase-Locked Loop Command
Bits.
These three bits encode the eight commands for the Digi-
tal Phase-Locked Loop. A channel or hardware reset dis-
ables the DPLL, resets the missing clock latches, sets the
Reset Clock Missing Command (010). Issuing this com-
mand disables the DPLL, resets the clock missing latches
in RR10, and forces a continuous Search mode state.
Disable DPLL Command (011). Issuing this command
disables the DPLL, resets the clock missing latches in
RR10, and forces a continuous Search mode state.
UM010901-0601
5-19