Z85233 Datasheet, PDF (189/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
The Z180™ Interfaced with the SCC at MHZ
(Continued)
initscc:
init0:
;initialize z180’s scc
;
initdma:
Table 14. Test Program – Z180/SCC DMA Transfer (Continued)
ld
hl,scctab
ld
a,(hl)
cp
0ffh
ret
z
out
(scc_cont),a
inc
hl
ld
a,(hl)
out
(scc_cont),a
inc
hl
jr
init0
; initialize scc
ld
hl,addrtab
;initialize DMA
ld
ld
otimr
ld
out0
ld
c,sar0l
b,dstat - sar0l
a,00001100b
(dmode),a
a,01001000b
ret
txend:
ld
a,00010100b
out0
(dstat),a
set
0,b
ei
ret
rxend:
ld
a,00100000b
out0
(dstat),a
set
1,b
ei
ret
;initialization data table for scc
;table format - register number, then value for the register
;and ends with 0ffh - since scc doesn’t have
;register 0ffh...
scctab:
db
09h
if scc_a
db
10000000b
else
db
01000000b
endif
db
04h
db
00000100b
;dmac0 - i/o to mem++
;1 mem wait, no i/o wait,
;should be EDGE for Tx DMA
;NOT level
;- because of DTR/REQ timing
;isr for dma1 int-complete tx
;disable dma1
;set status
;isr for dma0 int
;disable dma0
;set status
;select WR9
;reset ch a
;Reset Ch B
;select WR4
;async,x1,1stop,parity off
6-54
UM010901-0601