Z85233 Datasheet, PDF (305/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
Interfacing the ISCC™ to the 68000 and 8086
To start, the BCR write (first write to the ISCC after
RESET) is done with A7 = 1 (A1/A/B ISCC input at logic
high). This selects the wait option of the WAIT/RDY signal
to conform to the 8086 bus style. The AS signal
programming of the multiplexed bus was covered earlier.
The BCR is written with 86H to enable byte swapping,
select the sense of the byte swapping with respect to A0
(appropriate to this bus style), and select the Double Pulse
type of interrupt acknowledge.
When the ISCC™ begins DMA transfers, it communicates
requests for the bus through BUSREQ and BUSACK. The
8086 receives and grants bus requests through HOLD and
HLDA in the minimum mode and through RQ/GT in the
maximum mode. Depending upon the system
requirements, there could be more than one potential bus
master. Therefore, there is a requirement for a bus
arbitration circuit.
The minimum mode connection is relatively
straightforward. The maximum mode configuration
requires a translation of the ISCC BUSREQ and BUSACK
signals into/from the 8086 RQ/GT timed pulse style of
handshake. Refer to the information on the 8086 for
detailed application information.
The ISCC™ WAIT/RDY output is compatible with the 8086
clock generator RDY input except that one edge of the
signal must be synchronous with the 8086 clock. The
synchronization occurs through external circuitry. Refer to
the information on the 8086 for detailed application
information.
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UM010901-0601