Z85233 Datasheet, PDF (197/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
The Zilog Datacom Family with the 80186 CPU
RAM
Six 32-pin sockets are provided; they should be populated
in pairs, starting with the lower-numbered sockets, to allow
for 16-bit accesses. V_CC is provided at both pin 32 and pin
30 so that 28-pin 32K x 8 SRAMs can be installed in pins
3-30 of the sockets. Jumper block J19 allows decoding of
the Chip Select signals from A17-A16 for 32K x 8 SRAMs
or from A19-A18 for 128K x 8 SRAMs. The six standard
memory populations are:
One pair of 32K x 8 devices:
Two pairs of 32K x 8 devices:
Three pairs of 32K x 8 devices:
One pair of 128K x 8 devices:
Two pairs of 128K x 8 devices:
Three pairs of 128K x 8 devices:
64 Kbytes at 00000-0FFFF
128 Kbytes at 00000-1FFFF
192 Kbytes at 00000-2FFFF
256 Kbytes at 00000-3FFFF
512 Kbytes at 00000-7FFFF
768 Kbytes at 00000-BFFFF
J19 is factory set according to the size of the SRAMs
provided. For 32K x 8 SRAMs, jumpers are installed
between J19-J2 and J19-J3, and between J19-J5 and J19-
J6, with J19-J1 and J19-J4 left open. For 128K x 8 SRAMs,
jumpers are installed between J19-J1 and J19-J2, and
between J19-J4 and J19-J5, with J19-J3 and J19-J6 left
open.
32K x 8 SRAMs have cyclic/redundant addressing starting
at 40000, 80000, and C0000. The only configuration in
which this causes problems is with three pairs of 32K x 8
SRAMs and 27512 EPROMs; in this case, there is a
conflict in the range E0000-EFFFF. This conflict can be
avoided by any of the following means:
s Using two pairs of 32K x 8 SRAMs;
s Using one pair of 128K x 8 SRAMs;
s Using 27256 EPROMs, or
s Using 27512 EPROMs but programming the size of
/UCS like they are 27256s.
Since the /LCS output of the 80186 is not used, the LMCS
register in the 80186 is not written with any value.
Programming the Peripheral Chip Selects
The 80186 allows the /PCS6-/PCS0 pins, which in this
case select the various datacom controllers, to be
asserted for a selected 896-byte block of addresses. The
block may reside in either memory or I/O space depending
on the values programmed into the PACS and MPCS
registers, locations A4H and A8H of the 80186’s
Peripheral Control Block, respectively. The choice of
address space depends on the needs of the customer’s
application and the configuration of software supplied with
the board (Table 5).
Table 5. Three Standard Alternatives for Serial Controller Addressing
Basic Requirement
I/O Space
Memory Space, 32K x 8 SRAMS used
Memory Space, 128K x 8 SRAMs used
Base Address (PBA)
8000
38000
D8000
PACS value
0838
3838
D838
MPCS value
81B8
81F8
81F8
The three LSBs of the PACS value specify the
Ready/WAIT handling for the /PCS3-/PCS0 lines which
select the (E)SCC, ISCC, and (M)USC. The three LSBs of
the MPCS value specify the Ready/WAIT handling for the
/PCS4, 5, and 6 lines, which select the IUSC. Both fields
are shown here with the LSB’s 000, signifying that the
80186 should honor a WAIT on the external Ready/WAIT
signal, but that it should not provide any minimum wait.
Programming the Mid-Range Memory to Reset the
ISCC, IUSC, and (M)USC
A Reset puts the ISCC, IUSC, and (M)USC in a special
and unique state in which the first write to each device
implicitly goes to a Bus Configuration Register (BCR) that
controls the device’s basic bus operation; the BCR is not
accessible thereafter. So that this board can serve as a
complete development environment for customers’
software, it includes a means whereby software (e.g., the
debug monitor) can assert the /RESET input of these three
devices. Specifically, assertion of the /MCS2 output of the
80186 causes such a Reset.
The 81 in the MS Byte of the MPCS values, shown in Table
5, makes each of the /MCS3-/MCS0 pins correspond to a
2 Kbyte block of addresses in memory space. The actual
active pin addresses are determined by the value written
into the MMCS register; location A6H of the 80186'
Peripheral Control Block. Table 6 shows suggested
MMCS values as a function of the RAM chip size, and the
corresponding range of addresses for which any read or
write access causes the three controllers to be reset.
6-62
UM010901-0601