Z85233 Datasheet, PDF (30/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.3.2 Z85X30 Write Cycle Timing
The write cycle timing for the Z85X30 is shown in Figure 2- Historically, the NMOS/CMOS version latched the data
2 ^{6. The address on A//B and D//C, as well as the data on bus on the falling edge of /WR. However, many CPUs do}
D7-D0, is latched by the coincidence of /WR and /CE ac- not guarantee that the data bus is valid at the time when
tive. /CE must remain Low and /INTACK must remain High the /WR pin goes low, so the data bus timing was modified
throughout the cycle. A write cycle with D//C High does not to allow a maximum delay from the falling edge of /WR to
disturb the state of the pointers and a write cycle with D//C the latching of the data bus. On the Z85230, the AC Timing
Low resets the pointers to zero after the internal operation parameter #29 TsDW(WR), Write Data to /WR falling min-
is complete.
imum, has been changed to: /WR falling to Write Data Val-
id maximum. Refer to the AC Timing Characteristic section
of the Z85230 Product Specification for more information
regarding this change.
A//B, D//C
Address Valid
/INTACK
/CE
/WR
See Note
D7-D0
Note: Dotted line is ESCC only.
Data Valid
Figure 2-6. Z85X30 Write Cycle Timing
2.3.3 Z85X30 Interrupt Acknowledge Cycle Timing
The interrupt acknowledge cycle timing for the Z85X30 is the rising edge of PCLK (AC Spec #10). While /INTACK is
shown in Figure 2-7. The state of /INTACK is latched by Low, the state of A//B, /CE, D//C, and /WR are ignored.
/INTACK
/RD
D7-D0
Vector
Figure 2-7. Z85X30 Interrupt Acknowledge Cycle Timing
UM010901-0601
2-11