Z85233 Datasheet, PDF (25/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.2 Z80X30 INTERFACE TIMING (Continued)
Table 2-1. Z80X30 Register Map (Shift Left Mode)
AD5 AD4 AD3 AD2 AD1
WRITE
READ 8030
80C30/230*
WR15 D2 = 0
0
0
0
0
0
0
0
0
0
1
WR0B
WR1B
RR0B
RR1B
0
0
0
1
0
WR2
RR2B
0
0
0
1
1
WR3B
RR3B
0
0
1
0
0
WR4B
(RR0B)
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
WR5B
WR6B
WR7B
WR8B
WR9
WR10B
(RR1B)
(RR2B)
(RR3B)
RR8B
(RR13B)
RR10B
0
1
0
1
1
WR11B
(RR15B)
0
1
1
0
0
WR12B
RR12B
0
1
1
0
1
WR13B
RR13B
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
WR14B
WR15B
WR0A
WR1A
WR2
WR3A
RR14B
RR15B
RR0A
RR1A
RR2A
RR3A
1
0
1
0
0
WR4A
(RR0A)
1
0
1
0
1
WR5A
(RR1A)
1
0
1
1
0
WR6A
(RR2A)
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
WR7A
WR8A
WR9
WR10A
WR11A
WR12A
(RR3A)
RR8A
(RR13A)
RR10A
(RR15A)
RR12A
1
1
1
0
1
WR13A
RR13A
1
1
1
1
0
WR14A
RR14A
1
1
1
1
1
WR15A
RR15A
Notes:
The register names in ( ) are the values read out from that register location.
WR15, bit D2 enables status FIFO function (not available on NMOS).
WR7' bit D6 enables extend read function (only on ESCC).
* Includes 80C30/230 when WR15 D2=0.
80C30/230
WR15 D2=1
RR0B
RR1B
RR2B
RR3B
(RR0B)
(RR1B)
RR6B
RR7B
RR8B
(RR13B)
RR10B
(RR15B)
RR12B
RR13B
RR14B
RR15B
RR0A
RR1A
RR2A
RR3A
(RR0A)
(RR1A)
RR6A
RR7A
RR8A
(RR13A)
RR10A
(RR15A)
RR12A
RR13A
RR14A
RR15A
80230
WR15 D2=1
WR7' D6=1
RR0B
RR1B
RR2B
RR3B
(WR4B)
(WR5B)
RR6B
RR7B
RR8B
(WR3B)
RR10B
(WR10B)
RR12B
RR13B
(WR7’B)
RR15B
RR0A
RR1A
RR2A
RR3A
(WR4A)
(WR5A)
RR6A
RR7A
RR8A
(WR3A)
RR10A
(WR10A)
RR12A
RR13A
(WR7’A)
RR15A
2-6
UM010901-0601