Z85233 Datasheet, PDF (85/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Data Communication Modes
4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)
Once the buffer becomes empty, the Tx CRC Enable The initialization sequence for the transmitter in character-
bit is written for the next character.
oriented mode is shown in Table 4-5.
Enabling the CRC generator is not sufficient to control the
transmission of the CRC. In the SCC, this function is con-
trolled by the Tx Underrun/EOM bit, which is reset by the
processor and set by the SCC. When the transmitter un-
derruns (both the transmit buffer and Transmit Shift regis-
ter are empty) the state of the Tx Underrun/EOM bit deter-
mines the action taken by the SCC. If the Tx
Underrun/EOM bit is reset when the underrun occurs, the
transmitter sends the accumulated CRC and sets the Tx
Underrun/EOM bit to indicate this. This transition is pro-
grammed to cause an external/status interrupt, or the Tx
Underrun/EOM is available in RR0.
The Reset Tx Underrun/EOM Latch command is encoded
in bits D7 and D6 of WR0. For correct transmission of the
CRC at the end of a block of data, this command is issued
after the first character is written to the SCC but before the
transmitter underruns. The command is usually issued im-
mediately after the first character is written to the SCC so
that the CRC is sent if an underrun occurs inadvertently
during the block of data.
85X30
If WR7' bit D1 is set, the Reset Transmit Underrun/EOM
latch is automatically reset after the first byte is writ-
ten to the transmitter. This eliminates the need for the
CPU to issue this command. This feature can be par-
ticularly useful to applications using a DMA to write
data to the transmitter since there is no longer a need
to interrupt the data transfers to issue this command.
If the transmitter is disabled during the transmission of a
character, that character is sent completely. This applies
to both data and sync characters. However, if the transmit-
ter is disabled during the transmission of the CRC, the
16-bit transmission is completed, but the remaining bits
will come from the Sync registers rather than the remain-
der of the CRC.
There are two modem control signals associated with the
transmitter provided by the SCC: /RTS and /CTS.
The /RTS pin is a simple output that carries the inverted
state of the RTS bit (D1) in WR5.
Table 4-5. Transmitter Initialization in Character-
Oriented Mode
Reg Bit No
WR4 0,1
WR5 1
2
5,6
WR10 7
Description
selects parity (not typically used
insync modes)
RTS
selects CRC generator
selects number of bits per character
CRC preset value
At this point, the other registers should be initialized as nec-
essary. When all of this is completed, the transmitter is en-
abled by setting bit 3 of WR5 to one. Now that the transmit-
ter is enabled, the CRC generator is initialized by issuing the
Reset Tx CRC Generator command in WR0, bits 6-7.
4.3.2 Byte-Oriented Synchronous Receive
The receiver in the SCC searches for character synchroni-
zation only while it is in Hunt mode. In this mode the receiv-
er is idle except that it is searching the incoming data
stream for a sync character match.
In Hunt mode, the receiver shifts for each bit into the Re-
ceive Shift register. The contents of the Receive Shift reg-
ister are compared with the sync character (stored in an-
other register), repeating the process until a match occurs.
When a match occurs, the receiver begins transferring
bytes to the Receive FIFO.
The receiver is in Hunt mode when it is first enabled, and
it may be placed in Hunt mode by the processor issuing the
Enter Hunt Mode command in WR3. This bit (D4) is a com-
mand, so writing a 0 to it has no effect. The hunt status of
the receiver is reported by the Sync/Hunt bit in RR0.
Sync/Hunt is one of the possible sources of external/status
interrupts, with both transitions causing an interrupt. This
is true even if the Sync/Hunt bit is set as a result of the pro-
cessor issuing the Enter Hunt Mode command.
Once the sync character-oriented mode has been select-
ed, any of the four sync character lengths may be selected:
6 bits, 8 bits, 12 bits, or 16 bits.
The /CTS pin is ordinarily a simple input to the CTS bit in
RR0. However, if Auto Enables mode is selected, this pin
becomes an enable for the transmitter. That is, if Auto En-
ables is on and the /CTS pin is High, the transmitter is dis-
abled. While the /CTS pin is Low, the transmitter is enabled.
The Table 4-6 shows the write register bit setting for se-
lecting sync character length.
4-10
UM010901-0601