Z85233 Datasheet, PDF (18/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
General Description
1.4 PIN DESCRIPTIONS (Continued)
receive clock cycle in which the synchronous condition is
not latched. These outputs are active each time a synchro-
nization pattern is recognized (regardless of character
boundaries). In SDLC mode, the pins act as outputs and
are valid on receipt of a flag. The /SYNC pins switch from
input to output when monosync, bisync, or SDLC is pro-
grammed in WR4 and sync modes are enabled.
/DTR//REQA, /DTR//REQB. Data Terminal Ready/Re-
quest (outputs, active Low). These pins are programmable
(WR14, D2) to serve either as general-purpose outputs or
as DMA Request lines. When programmed for DTR func-
tion (WR14 D2=0), these outputs follow the state pro-
grammed into the DTR bit of Write Register 5 (WR5 D7).
When programmed for Ready mode, these pins serve as
DMA Requests for the transmitter.
ESCC and 85C30:
When used as DMA request lines (WR14, D2=1), the
timing for the deactivation request can be pro-
grammed in the added register, Write Register 7'
(WR7') bit D4. If this bit is set, the /DTR//REQ pin is de-
activated with the same timing as the /W/REQ pin. If
WR7' D4 is reset, the deactivation timing of /DTR//REQ
pin is four clock cycles, the same as in the Z85C30.
/W//REQA, /W//REQB. Wait/Request (outputs, open-drain
when programmed for Wait function, driven High or Low
when programmed for Ready function). These dual-pur-
pose outputs may be programmed as Request lines for a
DMA controller or as Wait lines to synchronize the CPU to
the SCC data rate. The reset state is Wait.
RxDA, RxDB. Receive Data (inputs, active High). These
input signals receive serial data at standard TTL levels.
/RTxCA, /RTxCB. Receive/Transmit Clocks (inputs, active
Low). These pins can be programmed to several modes of
operation. In each channel, /RTxC may supply the receive
clock, the transmit clock, the clock for the baud rate gener-
ator, or the clock for the Digital Phase-Locked Loop. These
pins can also be programmed for use with the respective
SYNC pins as a crystal oscillator. The receive clock may
be 1, 16, 32, or 64 times the data rate in asynchronous
modes.
TxDA, TxDB. Transmit Data (outputs, active High). These
output signals transmit serial data at standard TTL levels.
/TRxCA, /TRxCB. Transmit/Receive Clocks (inputs or out-
puts, active Low). These pins can be programmed in sev-
eral different modes of operation. /TRxC may supply the
receive clock or the transmit clock in the input mode or
supply the output of the Transmit Clock Counter (which
parallels the Digital Phase-Locked Loop), the crystal oscil-
lator, the baud rate generator, or the transmit clock in the
output mode.
PCLK. Clock (input). This is the master SCC clock used to
synchronize internal signals. PCLK is a TTL level signal.
PCLK is not required to have any phase relationship with
the master system clock.
IEI. Interrupt Enable In (input, active High). IEI is used with
IEO to form an interrupt daisy chain when there is more
than one interrupt driven device. A high IEI indicates that
no other higher priority device has an interrupt under ser-
vice or is requesting an interrupt.
IEO. Interrupt Enable Out (output, active High). IEO is High
only if IEI is High and the CPU is not servicing the SCC in-
terrupt or the SCC is not requesting an interrupt (Interrupt
Acknowledge cycle only). IEO is connected to the next
lower priority device’s IEI input and thus inhibits interrupts
from lower priority devices.
/INT. Interrupt (output, open drain, active Low). This signal
is activated when the SCC requests an interrupt. Note that
/INT is an open-drain output.
/INTACK. Interrupt Acknowledge (input, active Low). This
is a strobe which indicates that an interrupt acknowledge
cycle is in progress. During this cycle, the SCC interrupt
daisy chain is resolved. The device is capable of returning
an interrupt vector that may be encoded with the type of in-
terrupt pending. During the acknowledge cycle, if IEI is
high, the SCC places the interrupt vector on the databus
when /RD goes active. /INTACK is latched by the rising
edge of PCLK.
1.4.2 Pin Descriptions, (Z85X30 Only)
D7-D0. Data bus (bidirectional, tri-state). These lines carry
data and commands to and from the Z85X30.
/CE. Chip Enable (input, active Low). This signal selects
the Z85X30 for a read or write operation.
/RD. Read (input, active Low). This signal indicates a read
operation and when the Z85X30 is selected, enables the
Z85X30’s bus drivers. During the Interrupt Acknowledge cy-
cle, /RD gates the interrupt vector onto the bus if the Z85X30
is the highest priority device requesting an interrupt.
/WR. Write (input, active Low). When the Z85X30 is select-
ed, this signal indicates a write operation. This indicates
that the CPU wants to write command bytes or data to the
Z85X30 write registers.
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