Z85233 Datasheet, PDF (130/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Register Descriptions
generates an External/Status interrupt. Any odd number of _{5.3.2 Read Register 1}
transitions on the /DCD pin while another External/Status
interrupt condition. If the DCD IE is reset, this bit merely re-
ports the current, unlatched state of the /DCD pin.
RR1 contains the Special Receive Condition status bits
and the residue codes for the l-field in SDLC mode. Figure
5-20 shows the bit positions for RR1.
5
Bit 2: TX Buffer Empty status
This bit is set to 1 when the transmit buffer is empty. It is
reset while the CRC is sent in a synchronous or SDLC
mode and while the transmit buffer is full. The bit is reset
when a character is loaded into the transmit buffer.
Read Register 1
D7 D6 D5 D4 D3 D2 D1 D0
On the ESCC, the status of this bit is not related to the
Transmit Interrupt Status or the state of WR7' bit D5, but it
shows the status of the entry location of the Transmit
FIFO. This means more data can be written without being
overwritten. This bit is set to 1 when the entry location of
the Transmit FIFO is empty. It is reset when a character is
loaded into the entry location of the Transmit FIFO.
All Sent
Residue Code 2
Residue Code 1
Residue Code 0
Parity Error
Rx Overrun Error
CRC/Framing Error
This bit is always in the set condition after a hardware or
channel reset.
End of Frame (SDLC)
Figure 5-20. Read Register 1
For more information on this bit, refer to Section 2.4.8
“Transmit Interrupts and Transmit Buffer Empty bit”.
Bit 1: Zero Count status
If the Zero Count interrupt Enable bit is set in WR15, this
bit is set to one while the counter in the baud rate genera-
tor is at the count of zero. If there is no other External/Sta-
tus interrupt condition pending at the time this bit is set, an
External/Status interrupt is generated. However, if there is
another External/Status interrupt pending at this time, no
interrupt is initiated until interrupt service is complete. If the
Zero Count condition does not persist beyond the end of
the interrupt service routine, no interrupt is generated. This
bit is not latched High, even though the other External/Sta-
tus latches close as a result of the Low-to-High transition
on ZC. The interrupt routine checks the other External/Sta-
tus conditions for changes. If none changed, ZC was the
source. In polled applications, check the IP bit in RR3A for
a status change and then proceed as in the interrupt ser-
vice routine.
Bit 0: Receive Character Available
This bit is set to 1 when at least one character is available
in the receive data FIFO. It is reset when the receive data
FIFO is completely empty. A channel or hardware reset
empties the receive data FIFO.
On the ESCC, the status of this bit is independent of WR7'
bit D3.
Bit 7: End of Frame (SDLC) status
This bit is used only in SDLC mode and indicates that a
valid closing flag has been received and that the CRC Er-
ror bit and residue codes are valid. This bit is reset by is-
suing the Error Reset command. It is also updated by the
first character of the following frame. This bit is reset in any
mode other than SDLC.
Bit 6: CRC/Framing Error status
If a framing error occurs (in Asynchronous mode), this bit
is set (and not latched) for the receive character in which
the framing error occurred. Detection of a framing error
adds an additional one-half bit to the character time so that
the framing error is not interpreted as a new Start bit. In
Synchronous and SDLC modes, this bit indicates the re-
sult of comparing the CRC checker to the appropriate
check value. This bit is reset by issuing an Error Reset
command, but the bit is never latched. Therefore, it is al-
ways updated when the next character is received. When
used for CRC error status in Synchronous or SDLC
modes, this bit is usually set since most bit combinations,
except for a correctly completed message, result in a non-
zero CRC.
On the CMOS and ESCC, if the Status FIFO is enabled (re-
fer to the description in Write Register 15, bit D2 and the de-
scription in Read Register 7, bits D7 and D6), this bit reflects
the status stored at the exit location of the Status FIFO.
For details on this bit, refer to Section 2.4.7, The Receive
Interrupt.
Bit 5: Receiver Overrun Error status
This bit indicates that the Receive FIFO has overflowed.
Only the character that has been written over is flagged
with this error. When that character is read, the Error con-
dition is latched until reset by the Error Reset command.
UM010901-0601
5-23