Z85233 Datasheet, PDF (304/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

When the ISCC becomes a bus master during DMA
operations, RD and WR of the 8086 are tri-stated which
allows the corresponding ISCC signals to control the bus
transactions. The sense of RESET reverses, so the ISCC
RESET signal inverts from the reset applied to the 8086
from the clock state generator.
RD/WR and DS of the ISCC are inactive in this application
and tie high. They tie high through independent pull-ups
since these signals become active when the ISCC is bus
master during DMA transactions.
Assuming other devices in the system, the ISCC chip
enable input (CE) activates from a decode of the address.
In this example, the ISCC internally decodes addresses
A1 through A5 and uses A6 and A7, externally. Thus, the
address decode circuitry decodes address lines A0 and A8
and above. The decode of A0 for chip enable places the
ISCC as an 8-bit peripheral on the lower byte of the bus.
A0 and the upper level address lines (including A6 and A7)
demultiplex from the 8086 address/data bus through a
latch strobed by ALE.
The demultiplexed addresses A6 and A7 connect to
A0/SCC/DMA and A1/A/B, respectively, of the ISCC to
control selection of the DMA and SCC channels A and B.
This connects through the tri-state drivers. They enable
when the 8086 is the bus master and disable when the
ISCC is bus master. This prevents the ISCC from
improperly driving the system address bus since
A0/SCC/DMA and A1/A/B become active outputs when
the ISCC is the bus master.
The address map for the ISCC appears in Table A-6 for
this application.
Table 44. ISCC Address Map
A0 A1-A5 A6
1xx
0-0
0-1
0-1
A7 Registers Addressed
x ISCC not enabled
x DMA Registers per A1 - A5
1 SCC Core Channel A
Registers
0 SCC Core Channel B
Registers
Since A0 specifies the lower byte of the bus and includes
the chip enable decode, the internal ISCC register
addresses decode without A0. Thus, Table 6 implies that
the Left Shift address decode selection is made for both
the SCC and DMA sections of the ISCC. The left shift
selection is the default selection after reset. Left/Right Shift
selection programming is discussed later.
Application Note
Interfacing the ISCC™ to the 68000 and 8086
The ALE signal of the 8086 applies to AS of the ISCC
through an inverting tri-state buffer. The buffer disables
when the ISCC becomes a bus master during DMA
transactions. This prevents conflicts since ALE remains
active even when the 8086 is in the HOLD mode during
DMA transfers. Now, the ISCC AS is an active output. The
address strobe for the demultiplexing latch of addresses
A0 through A15 connects on the ISCC side of the ALE tri-
state buffer. This allows the latch to serve two functions; to
hold either the 8086 or the ISCC address when it is bus
master.
After reset, ALE is active and the tri-state buffer enabled.
This supplies address strobes to the ISCC. The presence
of one of these address strobes, before writing to the BCR,
programs the ISCC to the multiplexed bus mode of
operation. The ISCC chip enable (CE) can be inactive and
still recognize an address strobe (AS) before the BCR
write (Figure 4 shows open latches when the input strobe
is low).
When the ISCC is bus master during DMA transactions,
BHE generates from A0. This is done from the output of
the lower order address latch through an inverting tri-state
driver. This driver enables only when the ISCC is the bus
master. Whole word transfers are not done by the ISCC
DMA, thus, BHE generated for the ISCC is always the
inverse of A0.
The upper bus system address lines demultiplex from the
8086 and the ISCC in separate latches. Like the 68000
example, high order address lines from the ISCC latch via
UAS (upper address strobe). The separate latches drive
the same upper order address lines. A16 from the ISCC
connects to the corresponding A16 address bus line as
derived from the 8086. The output of the two latches
alternately enable depending upon bus mastership.
The diagram shows INT from the ISCC connected to the
8086 INTR input via an inverter since these signals are of
opposite sense. In actual practice, the ISCC interrupt
request is first processed by an interrupt priority circuit.
INTA (Interrupt Acknowledge) of the 8086 connects
directly to the INTACK input of the ISCC. Conforming to
the 8086 style of interrupt acknowledge, the ISCC is
programed to the Double Pulse Interrupt Acknowledge
type. When this selection occurs, the ISCC responds to
two interrupt acknowledge pulses. The first pulse is
recognized but no action follows. The second pulse
causes the ISCC to go active on the data bus and return
the interrupt vector to the CPU. This action also takes
place with the Single Pulse Interrupt Acknowledge type
selection, except that the bus goes active with the first and
only interrupt acknowledge pulse.
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