Z85233 Datasheet, PDF (240/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

APPLICATION NOTE
1
USING SCC WITH Z8000 IN SDLC PROTOCOL
11
INTRODUCTION
This application note describes the use of the Z8030 Serial
Communications Controller (SCC) with the Z8000™ CPU
to implement a communications controller in a
Synchronous Data Link Control (SDLC) mode of
operation. In this application, the Z8002 CPU acts as a
controller for the SCC. This application note also applies to
the non-multiplexed Z8530.
One channel of the SCC communicates with the remote
station in Half Duplex mode at 9600 bits/second. To test
this application, two Z8000 Development Modules are
used. Both are loaded with the same software routines for
initialization and for transmitting and receiving messages.
The main program of one module requests the transmit
routine to send a message of the length indicated by
“COUNT” parameter. The other system receives the
incoming data stream, storing the message in its resident
memory.
DATA TRANSFER MODES
The SCC system interface supports the following data
transfer modes:
s Polled Mode. The CPU periodically polls the SCC
status registers to determine if a received character is
available, if a character is needed for transmission, and
if any errors have been detected.
s Interrupt Mode. The SCC interrupts the CPU when
certain previously defined conditions are met.
s Block/DMA Mode. Using the Wait/Request (/W//REQ)
signal, the SCC introduces extra wait cycles in order to
synchronize the data transfer between a controller or
DMA and the SCC.
The example given here uses the block mode of data
transfer in its transmit and receive routines.
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