Z85233 Datasheet, PDF (196/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
The Zilog Datacom Family with the 80186 CPU
Push buttons are provided for Reset and Non-Maskable addresses of the datacom controllers are programmed in
Interrupt (NMI). A means to generate an NMI, in response the 80186 for the /PCS6-/PCS0 outputs, as a block of
8 ^{to a Start bit received from the user’s PC or terminal, is 128x7=896 bytes starting at a 1 Kbyte boundary. The}
also provided. The first transmitted Start bit on the RS-232. block can be in I/O space or in a part of memory space that
Console connector J1, after a Reset, also produces an is not used for SRAM or EPROM. The starting 1 Kbyte
NMI; this feature can be used to find which serial controller boundary is called (PBA) in the following sections.
channel is connected to the Console connector.
RAM extends upward from address 0.
Address Map
EPROM is located at the highest addresses, and its size is
programmable in the 80186 for the /UCS output. The
Using 128K x 8 SRAMs and 64K x 8 EPROMs, the
address map might be as shown in Table 3.
RAM
(E)SCC
ISCC
(M)USC
IUSC
ISCC-IUSC-(M)USC Reset
27512 EPROM
Table 3. Suggested Address Map
00000-BFFFF
D8000, 2, 4, 6 or D8000-D803E (even addrs only)
D8080-D80FE (even addrs only)
D8100-D81FF
D8200-D837F
DB000-DB7FF (if enabled)
E0000-FFFFF
EPROM
Two 28-pin EPROM sockets are provided; both must be
populated in order to handle the 80186’s 16-bit instruction
fetches. Jumper header J18 allows the sockets to be
compatible with 2764s, 27128s, 27256s, or 27512s; it is
jumpered at the factory to match the EPROMs provided.
For 27512s only, jumper J18-J2 to J18-J3 and leave J18-
J1 open. For 2764s, 27128s, or 27256s, jumper J18-J2 to
J18-J1 and leave J18-J3 open.
Note: J18 connects pin 1 of both sockets to either A16 or
Vcc. This is done because for 2764s, 27128s, and 27256s,
pin 1 is Vpp which may require a high voltage and/or draw
more current than a normal logic input. For 2764s and
27128s, a similar jumper might be provided in some
designs for pin 27 (/PGM). As long as the address for /UCS
is programmed as described in the next paragraph, A15
(which is connected to pin 27) is High whenever /UCS is
Low, so that 2764s and 27128s operate correctly.
The first code executed after Reset should program the
80186’s Chip Select Control Registers to set up the
address ranges for which outputs like /UCS and /PCS6-
/PCS0 are asserted. In particular, the UMCS register
(address A0H within the 80186’s Peripheral Control Block)
must be programmed to correspond to the size of
EPROMs used (Table 4).
Table 4. EPROM Address Ranges
EPROM
Type
UMCS Value
2764
27128
27256
27512
EPROM
FC3C
F83C
F03C
E03C
Address
Range
FC000-FFFFF
F8000-FFFFF
F0000-FFFFF
E0000-FFFFF
The three LSBs of the above UMCS values are all 100,
which signifies no external Ready/WAIT is used and no
wait states are required. If the EPROMs are not fast
enough for no-wait-state operation, making the three LSBs
101, 110, or 111 extends EPROM cycles by 1, 2, or 3 wait
states, respectively.
UM010901-0601
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