Z85233 Datasheet, PDF (53/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.5 BLOCK/DMA TRANSFER (Continued)
/DS or /WR
to Tx Buffer
Tx Buffer Empty
Full
Empty
/W//REQ
(=WAIT)
Figure 2-24. Wait On Transmit Timing
This allows the use of a block move instruction to transfer
the transmit data. In the case of the Z80X30, /WAIT will go
active in response to /DS going active, but only if WR8 is
being accessed and a write is attempted. In all other cas-
es, /WAIT remains open-drain. In the case of the Z85X30,
/WAIT goes active in response to /WR going active, but
only if the data buffer is being accessed, either directly or
via the pointers. The /WAIT pin is released in response to
the falling edge of PCLK. Details of the timing are shown
in Figure 2-25.
Care must be taken when using this function, particularly
at slow transmission speed. The /WAIT pin stays active as
long as the transmit buffer stays full, so there is a possibil-
ity that the CPU may be kept waiting for a long period.
/TRxC
PCLK
/WAIT
Figure 2-25. Wait On Transmit Timing
SYNC Modes
ASYNC Modes
2-34
UM010901-06
01