Z85233 Datasheet, PDF (44/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.4.8 Transmit Interrupts and Transmit Buffer ^{byte is loaded into the Transmit Shift Register, but before}
Empty Bit
the last bit of the second CRC byte has cleared the Trans-
Transmit interrupts are controlled by Transmit Interrupt
Enable bit (D1) in WR1. If the interrupt capabilities of the
mit Shift Register, then data was written while the CRC
was being sent.
2
SCC are not required, polling may be used. This is select-
ed by disabling transmit interrupts and polling the Transmit
Buffer Empty bit (TBE) in RR0. When the TBE bit is set, a
character may be written to the SCC without fear of writing
over previous data. Another way of polling the SCC is to
enable transmit interrupts and then reset Master Interrupt
Enable bit (MIE) in WR9. The processor may then poll the
IP bits in RR3A to determine when the transmit buffer is
empty. Transmit interrupts should also be disabled in the
case of DMA transfer of the transmitted data.
2.4.8.2 Transmit Interrupt and Transmit Buffer Empty
bit on the ESCC
The ESCC has a 4-byte deep Transmit FIFO, while the
NMOS/CMOS SCC is just 1-byte deep. For this reason,
the generation of transmit interrupts is slightly different
from that of the NMOS/CMOS SCC version. The ESCC
has two modes of transmit interrupt generation, which are
programmed by bit D5 of WR7'. One transmit mode gener-
ates interrupts when the entry location (the location the
CPU writes data) of the Transmit FIFO is empty. This al-
Because the depth of the transmitter buffer is different be-
tween the NMOS/CMOS version of the SCC and ESCC,
generation of the transmit interrupt is slightly different. The
following subsections describe transmit interrupts.
lows the ESCC response to be tailored to system require-
ments for the frequency of interrupts and the interrupt re-
sponse time. On the other hand, the Transmit Buffer
Empty (TBE) bit on the ESCC will respond the same way
in each mode, in which the bit will become set when the
Note: For all interrupt sources, the Master Interrupt Enable
(MIE) bit, WR9 bit D3, must be set for the device to gener-
ate a transmit interrupt.
entry location of the Transmit FIFO is empty. The TBE bit
is not directly related to the transmit interrupt status nor the
state of WR7' bit D5.
2.4.8.1 Transmit Interrupts and Transmit Buffer Empty
Bit on the NMOS/CMOS
The NMOS/CMOS version of the SCC only has a one byte
deep transmit buffer. The status of the transmit buffer can
be determined through TBE bit in RR0, bit D2, which
shows whether the transmit buffer is empty or not. After a
hardware reset (including a hardware reset by software),
or a channel reset, this bit is set to 1.
While transmit interrupts are enabled, the NMOS/CMOS
version sets the Transmit Interrupt Pending (TxIP) bit
whenever the transmit buffer becomes empty. This means
that the transmit buffer must be full before the TxIP can be
set. Thus, when transmit interrupts are first enabled, the
TxIP will not be set until after the first character is written
to the NMOS/CMOS. In synchronous modes, one other
condition can cause the TxIP to be set. This occurs at the
end of a transmission after the CRC is sent. When the last
bit of the CRC has cleared the Transmit Shift Register and
the flag or sync character is loaded into the Transmit Shift
Register, the NMOS/CMOS version sets the TxIP and TBE
bit. Data for a second frame or block transmission may be
written at this time.
The TxIP is reset either by writing data to the transmit buff-
er or by issuing the Reset Tx Int command in WR0. Ordi-
narily, the response to a transmit interrupt is to write more
data to the device; however, the Reset Tx Int command
should be issued in lieu of data at the end of a frame or a
block of data where the CRC is to be sent next.
Note: A transmit interrupt may indicate that the packet has
terminated illegally, with the CRC byte(s) overwritten by
the data. If the transmit interrupt occurs after the first CRC
When WR7' D5=1 (the default case), the ESCC will gener-
ate a transmit interrupt when the Transmit FIFO becomes
completely empty. The transmit interrupt occurs when the
data in the exit location of the Transmit FIFO loads into the
Transmit Shift Register and the Transmit FIFO becomes
completely empty. This mode minimizes the frequency of
transmit interrupts by writing 4 bytes to the Transmit FIFO
upon each entry to the interrupt will become set when
WR7' D5=1. The TBE bit RR0 bit D2 will become set when-
ever the entry location of the Transmit FIFO becomes
empty. The TBE bit will reset when the entry location be-
comes full. The TBE bit in a sense translates to meaning
“Transmit Buffer Not Full” for the ESCC only, as the TBE
bit will become set whenever the entry location of the
Transmit FIFO becomes empty. This bit may be polled at
any time to determine if a byte can be written to the FIFO.
Figure 2-17 illustrates when the TBE bit will become set.
WR7' bit D5 is set to one by a hardware or channel reset.
When WR7' D5=0, the TxIP bit is set when the entry lo-
cation of the Transmit FIFO becomes empty. In this
mode, only one byte is written to the Transmit FIFO at a
time for each transmit interrupt. The ESCC will generate
transmit interrupts when there are 3 or fewer bytes in the
FIFO, and will continue to do so until the FIFO is filled.
When WR7' D5=0, the transmit interrupt is reset momen-
tarily when data is loaded into the entry location of the
Transmit FIFO. Transmit interrupt is not generated when
the entry location of the Transmit FIFO is filled. The trans-
mit interrupt is generated when the data is pushed down
the FIFO and the entry location becomes empty (approx-
imately one PCLK time). Figure 2-18 illustrates when the
transmit interrupts will become set when WR7' D5=0.
Again, the TBE bit is not dependent on the state of WR7'
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