Z85233 Datasheet, PDF (140/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
Interfacing Z80^® CPUs to the Z8500 Peripheral Family
INPUT/OUTPUT CYCLES
Although Z8500 peripherals are designed to be as All setup and pulse width times for the Z8500 peripherals
6 ^{universal as possible, certain timing parameters differ from are met by the standard Z80A timing. In determining the}
the standard Z80 timing. The following sections discuss interface necessary, the /CE signal to the Z8500
the I/O interface for each of the Z80 CPUs and the Z8500 peripherals is assumed to be the decoded address
peripherals. Figure 9 depicts logic for the Z80A CPU to qualified with the /IORQ signal.
Z8500 peripherals (and Z80B CPU to Z8500A peripherals)
I/O interface as well as the Interrupt Acknowledge ^{Figure 4 shows the minimum Z80A CPU to Z8500}
interface. Figures 4 and 7 depict some of the logic used to ^{peripheral interface timing for I/O cycles. If additional Wait}
interface the Z80H CPU to the Z8500 and Z8500A ^{states are needed, the same number of Wait states can be}
peripherals for the I/O and Interrupt Acknowledge ^{inserted for both I/O Read and Write cycles to simplify}
interfaces. The logic required for adding additional Wait ^{interface logic. There are several ways to place the Z80A}
states into the timing flow is not discussed in the following ^{CPU into a Wait condition (such as counters or shift}
sections.
registers to count system clock pulses), depending upon
whether or not the user wants to place Wait states in all
Z80A CPU to Z8500 Peripherals
I/O cycles, or only during Z8500 I/O cycles. Tables 3 and
No additional Wait states are necessary during the I/O
cycles, although additional Wait states can be inserted to
compensate for timing delays that are inherent in a
system. Although the Z80A timing parameters indicate a
negative value for data valid prior to /WR, this is a worse
than “worst case” value. This parameter is based upon the
longest (worst case) delay for data available from the
falling edge of the CPU clock minus the shortest (best
4 list the Z8500 peripheral and the Z80A CPU timing
parameters (respectively) of concern during the I/O cycles.
Tables 5 and 6 list the equations used in determining if
these parameters are satisfied. In generating these
equations and the values obtained from them, the required
number of Wait states was taken into account. The
reference numbers in Tables 3 and 4 refer to the timing
diagram in Figure 4.
case) delay for CPU clock High to /WR low. The negative
value resulting from these two parameters does not occur
because the worst case of one parameter and the best
case of the other do not occur within the same device. This
indicates that the value for data available prior to /WR will
always be greater than zero.
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