Z85233 Datasheet, PDF (230/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
Serial Communication Controller (SCC^™): SDLC Mode of Operation
Notes on Figure 1:
4. Transmit Buffer Empty Interrupt for data 42H. Data
0FFH is written to the Transmit Buffer at this point.
1. The SCC has two possible idle states, Mark idle
(contiguous logic 1) or Flag idle (repeating flag pattern
5. Transmit Buffer Empty Interrupt for data 0FFH. Data
1
7EH). In this figure, the SCC has to be switched to flag
42H is written to the Transmit Buffer at this point.
idle in order to send the opening flag of the frame.
Care must be taken not to put the first data byte (in this ^{6. The time between interrupts depends on the data}
case, address 81H) into the Transmit Buffer too soon
character length and the number of zero insertions in
after the switchover from Mark idle to Flag idle has
the character. For 8 bits/character it can vary between
been made; otherwise, the data may be loaded into
8 and 10 bit-times. The particular instance shown
the Transmit Shift Register before the flag is loaded.
corresponds to the single zero insertion when the byte
To ensure that this cannot happen, a delay must be
0FFH is transmitted.
executed before the first data byte is put into the
buffer. The delay time is dependent on the data rate
and a safe minimum duration is 8 bit-times.
7. Transmit Buffer Empty Interrupt for data 42H. Since
this is the last byte to be transmitted, the Reset
Transmit Interrupt Pending command is issued
2. Transmit Buffer Empty Interrupt for 81H. At this point
instead of writing another byte to the Transmit Buffer.
the data has just been transferred to the Transmit Shift
Register and data 42H is written to the Transmit
Buffer.
8. Transmitter Underrun/EOM Interrupt. This occurs
when both the Transmit Shift Register and the
Transmit Buffer are empty. It is an External/Status
3. The time between the first data byte being transferred
interrupt. The data sent when this occurs is
to the Shift Register and the first bit appearing at the
summarized in the table below:
TxD pin is always six bit-times.
Abort/Flag on
Underrun bit
0
1
0
1
Tx Underrun/EOM Latch
State when Underrun occurs
Reset
Reset
Set
Set
Data
Sent
CRC and Flag
Abort and Flag
Flags
Flags
9. The transmitted CRC is 16 bits long provided that
there are no zero insertions. In theory it could be as
long as 19 bits.
frame is to be transmitted, the first character of the
next frame can be loaded. The two frames will then be
separated by a single flag (Back-to-back frame).
10. The last interrupt generated occurs after the CRC is
shifted out of the transmitter and a flag is loaded to be
sent. It is a Transmit Buffer Empty Interrupt. If another
11. If the SCC is set up for mark on idle and a new
character is not loaded when the last interrupt occurs,
only a single flag is sent.
UM010901-0601
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