Z85233 Datasheet, PDF (41/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.4 INTERFACE PROGRAMMING (Continued)
WR1
D4 D3 D2
Parity is special condition
00 Receive Interrupt Disabled
01 Rx INT On First Character or Special Condition
10 Rx INT On All Receive Characters or Special Condition
11 Rx INT On Special Condition Only
Figure 2-14. Write Register 1 Receive Interrupt Mode Control
2.4.7.1 Receive Interrupt on the ESCC
On the ESCC, one other bit, WR7' bit D2, also affects the
interrupt operation.
WR7' D3=0, a receive interrupt is generated when one
byte is available in the FIFO. This mode is selected after
reset and maintains compatibility with the SCC. Systems
with a long interrupt response time can use this mode to
generate an interrupt when one byte is received, but still al-
low up to seven more bytes to be received without an over-
run error. By polling the Receive Character Available bit,
RR0 D0, and reading all available data to empty the FIFO
before exiting the interrupt service routine, the frequency
of interrupts can be minimized.
WR7' D3=1, the ESCC generates an interrupt when there
are four bytes in the Receive FIFO or when a special con-
dition is received. By setting this bit, the ESCC generates
a receive interrupt when four bytes are available to read
from the FIFO. This allows the CPU not to be interrupted
until at least four bytes can be read from the FIFO, thereby
minimizing the frequency of receive interrupts. If four or
more bytes remain in the FIFO when the Reset Highest
IUS command is issued at the end of the service routine,
another receive interrupt is generated.
When a special receive condition is detected in the top four
bytes, a special receive condition interrupt is generated
immediately. This feature is intended to be used with the
Interrupt On All Receive Characters and Special Condition
mode. This is especially useful in SDLC mode because the
characters are contiguous and the reception of the closing
flag immediately generates a special receive interrupt. The
generation of receive interrupts is described in the follow-
ing two cases:
Case 1: Four Bytes Received with No Errors. A receive
character available interrupt is triggered when the four
bytes in receive data FIFO (from the exit side) are full
and no special conditions have been detected. There-
fore, the interrupt service routine can read four bytes
from the data FIFO without having to read RR1 to check
for error conditions.
Case 2: Data Received with Error Conditions. When any
of the four bytes from the exit side in the receive error FIFO
indicate an error has been detected, a Special Receive
condition interrupt is triggered without waiting for the byte
to reach the top of the FIFO. In this case, the interrupt ser-
vice routine must read RR1 first before reading each data
byte to determine which byte has the special receive con-
dition and then take the appropriate action. Since, in this
mode, the status must be checked before the data is read,
the data FIFO is not locked and the Error Reset command
is not necessary.
Note: The above cases assume that the receive IUS bit is
reset to zero in order for an interrupt to be generated.
WR7' D3 should be written zero when using Interrupt on
First Character and Special Condition or Interrupt on Spe-
cial Condition Only. See the description for Interrupt on All
Characters or Special Condition mode for more details on
this feature.
Note: The Receive Character Available Status bit, RR0
D0, indicates if at least one byte is available in the Receive
FIFO, independent of WR7' D3. Therefore, this bit can be
polled at any time for status if there is data in the Receive
FIFO.
2.4.7.2 Receive Interrupts Disabled
This mode prevents the receiver from requesting an inter-
rupt. It is used in a polled environment where either the
status bits in RR0 or the modified vector in RR2 (Channel
B) is read. Although the receiver interrupts are disabled,
the interrupt logic can still be used to provide status.
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