Z85233 Datasheet, PDF (36/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
ESCC:
The External/status interrupts have several sources which
The receive interrupt request is either caused by a re- may be individually enabled in WR15. The sources are
2 ^{ceive character available or a special condition. When zero count, /DCD, Sync/Hunt, /CTS, transmitter under-}
the receive character available interrupt is generated, run/EOM and Break/Abort.
it is dependent on WR7' bit D3. If WR7' D3=0, the re-
ceive character available interrupt is generated when 2.4.4 Interrupt Control
one character is loaded into the FIFO and is ready to
be read. If WR7' D3=1, the receive character available
interrupt is generated when four bytes are available to
be read in the receive data FIFO. The programmed val-
ue of WR7' D5 also affects how DMA requests are gen-
erated. See Section 2.5 for details.
In addition to the MIE bit that enables or disables all SCC
interrupts, each source of interrupt in the SCC has three
control/status bits associated with it. They are the Interrupt
Enable (IE), Interrupt Pending (IP), and Interrupt-Under-
Service (IUS). Figure 2-10 shows the SCC interrupt
structure.
Note: If the ESCC is used in SDLC mode, it enables the
SDLC Status FIFO to affect how receive interrupts are
generated. If this feature is used, read Section 4.4.3 on the
SDLC Anti-Lock Feature.
Interrupt Vector
The special conditions are Receive FIFO overrun,
CRC/framing error, end of frame, and parity. If parity is in-
cluded as a special condition, it is dependent on WR1 D2.
The special condition status can be read from RR1.
On the NMOS/CMOS versions, set the IP bit whenever the
transmit buffer becomes empty. This means that the trans-
mit buffer was full before the transmit IP can be set.
ESCC:
The transmit interrupt request has only one source
and is dependent on WR7' D5. If the IP bit WR7' D5=0,
it is set when the transmit buffer becomes completely
empty. If IP bit WR7' D5=1, the transmit interrupt is
generated when the entry location of the FIFO is emp-
ty. Note that in both cases the transmit interrupt is not
set until after the first character is written to the ESCC.
For more information on Transmit Interrupts, see Section
2.4.8 for details.
IE
MIE
DLC
IP
IUS
IEI /INT /INTACK IEO
from Pullup
Resistor or IEO
line of Higher
Priority Device
To CPU
From
CPU
Status
Decoder
To IEI Input of
Lower Priority
Device
Figure 2-10. Peripheral Interrupt Structure
Figure 2-11 shows the internal priority resolution method
to allow the highest priority interrupt to be serviced first.
Lower priority devices on the external daisy chain can be
prevented from requesting interrupts via the Disable Lower
Chain bit in WR9 D2.
from
IEI
Pin
Channel A
Receiver
(Highest Priority)
IEI
IEO
IE IP IUS
Channel A
Transmitter
IEI
IEO
IE IP IUS
Channel A
External/Status
Conditions
IEI
IEO
IE IP IUS
UM010901-0601
Channel B
Receiver
IEI
IEO
IE IP IUS
Channel B
Transmitter
IEI
IEO
IE IP IUS
Channel B
External/Status
Conditions
(Lowest
IEI _Priority) IEO
To
IEO
Pin
IE IP IUS
Figure 2-11. Internal Priority Resolution
2-17