Z85233 Datasheet, PDF (141/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
Interfacing Z80^® CPUs to the Z8500 Peripheral Family
INPUT/OUTPUT CYCLES (Continued)
Worst Case
6. TsA(WR)
1. TsA(RD)
2. TdA(DR)
TsCEI(WR)
TsCEI(RD)
4. TwRDI
8. TwWRI
3. TdRDf(DR)
7. TsDW(WR)
Table 2. Z8500 Timing Parameters I/O Cycles
Address to /WR to Low Setup
Address to /RD Low Setup
Address to Read Data Valid
/CE Low to /WR Low Setup
/CE Low to /RD Low Setup
/RD Low Width
/WR Low Width
/RD Low to Read Data Valid
Write Data to /WR Low Setup
Min
Max
80
80
590
ns
ns
390
390
255
0
Units
ns
ns
ns
ns
ns
ns
Worst Case
TcC
TwCh
TfC
TdCr(A)
TdCr(RDf)
TdCr(IORQf)
TdCr(WRf)
5. TsD(Cf)
Table 3. Z80A Timing Parameters I/O Cycles
Clock Cycle Period
Clock Cycle High Width
Clock Cycle Fall Time
Clock High to Address Valid
Clock High to /RD Low
Clock High to /IORQ Low
Clock High to /WR Low
Data to Clock Low Setup
Min
Max
250
110
30
110
85
75
65
50
Units
ns
ns
ns
ns
ns
ns
ns
ns
Z8500
Parameter
TsA(RD)
TdA(DR)
TdRDf(DR)
TwRD1
TsA(WR)
TsDW(WR)
TwWR1
.
Z80A
Parameter
TsD(Cf)
Table 4. Parameter Equations
Z80A
Equation
TcC-TdCr(A)
3TcC+TwCh-TdCr(A)-TsD(Cf)
2TcC+TwCh-TsD(Cf)
2TcC+TwCh+TfC-TdCr(RDf)
TcC-TdCr (A)
2TcC+TwCh+TfC-TdCr(WRf)
Value
140 min
800 min
460 min
525 min
140 min
>0 min
560 min
Table 5. Parameter Equations
Z8500
Equation
3TcC+TwCh-TdCr(A)-TdA(DR)
/RD
2TcC+TwCh-TdCr(RDf)-TdRD(DR)
Value
160 min
135 min
Units
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
6-6
UM010901-0601