Z85233 Datasheet, PDF (26/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
Table 2-2. Z80X30 Register Map (Shift Right Mode)
AD4 AD3 AD2 AD1 AD0
WRITE
READ 8030
80230
80C30/230*
80C30/230
WR15 D2=1
2
WR15 D2 = 0 WR15 D2=1
WR7' D6=1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
WR0B
WR0A
WR1B
WR1A
WR2
WR2
RR0B
RR0A
RR1B
RR1A
RR2B
RR2A
RR0B
RR0A
RR1B
RR1A
RR2B
RR2A
RR0B
RR0A
RR1B
RR1A
RR2B
RR2A
0
0
1
1
0
WR3B
RR3B
RR3B
RR3B
0
0
1
1
1
WR3A
RR3A
RR3A
RR3A
0
1
0
0
0
WR4B
(RR0B)
(RR0B)
(WR4B)
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
WR4A
WR5B
WR5A
WR6B
WR6A
WR7B
(RR0A)
(RR1B)
(RR1A)
(RR2B)
(RR2A)
(RR3B)
(RR0A)
(RR1B)
(RR1A)
RR6B
RR6A
RR7B
(WR4A)
(WR5B)
(WR5A)
RR6B
RR6A
RR7B
0
1
1
1
1
WR7A
(RR3A)
RR7A
RR7A
1
0
0
0
0
WR8B
RR8B
RR8B
RR8B
1
0
0
0
1
WR8A
RR8A
RR8A
RR8A
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
WR9
WR9
WR10B
WR10A
WR11B
WR11A
(RR13B)
(RR13A)
RR10B
RR10A
(RR15B)
(RR15A)
(RR13B)
(RR13A)
RR10B
RR10A
(RR15B)
(RR15A)
(WR3B)
(WR3A)
RR10B
RR10A
(WR10B)
(WR10A)
1
1
0
0
0
WR12B
RR12B
RR12B
RR12B
1
1
0
0
1
WR12A
RR12A
RR12A
RR12A
1
1
0
1
0
WR13B
RR13B
RR13B
RR13B
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
WR13A
WR14B
WR14A
WR15B
WR15A
RR13A
RR14B
RR14A
RR15B
RR15A
RR13A
RR14B
RR14A
RR15B
RR15A
RR13A
(WR7’B)
(WR7’A)
RR15B
RR15A
Notes:
The register names in ( ) are the values read out from that register location.
WR15 bit D2 enables status FIFO function (not available on NMOS).
WR7' bit D6 enables extend read function (only on ESCC).
* Includes 80C30/230 when WR15 D2=0.
UM010901-0601
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