Z85233 Datasheet, PDF (56/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
With only one exception, the /REQ pin directly follows the PCLK cycle. The DMA uses this falling edge on /REQ to
state of the transmit buffer (for the ESCC as programmed write the first character of the next frame to the SCC. In the
2 ^{by WR7' D5) in this mode. The SCC generates only one case of the Z80X30, /REQ goes High in response to the}
falling edge on /REQ per character requested and the tim- falling edge of DS, but only if the appropriate channel
ing for this is shown in Figure 2-29.
transmit buffer in the SCC is accessed. This is shown in
Figure 2-25. In the case of the Z85X30, /REQ goes High in
The one exception occurs in synchronous modes at the _{response to the falling edge of /WR, but only when the ap-}
end of a CRC transmission. At the end of a CRC transmis- _{propriate channel transmit buffer in the SCC is accessed.}
sion, when the closing flag or sync character is loaded into _{This is shown in Figure 2-30.}
the Transmit Shift Register, /REQ is pulsed High for one
/AS
AD7-AD0
/DS
WR8 Transmit Data
PCLK
/REQ
(/DTR//REQ)
/REQ
(/W//REQ)
Figure 2-29. Z80X30 Transmit Request Release
/WR
D7-D0
PCLK
/REQ
(/DTR//REQ)
/REQ
(/W//REQ)
Transmit Data
Figure 2-30. Z85X30 Transmit Request Release
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