Z85233 Datasheet, PDF (312/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

ASYNCHRONOUS MODE
Q. Can the Sync Character Load Inhibit function strip
characters in Asynchronous mode if not disabled?
A. Yes. If not disabled it will strip any characters which
match the value in the sync character register. Always
disable this function in asynchronous mode (WR3, bit
D1).
Q. What controls the DTR/WREQ pin?
A. The DTR pin follows the D7 bit in WR5 (inverse) as a
Data Terminal Ready pin, or it is a DMA request line
(WREQ). The bit can be set or reset by writing to WR5.
Q. How is the Asynchronous mode selected?
A. The Asyn mode is selected by programming the num-
ber of stop bits in write register 4.
Q. How are receiver breaks handled?
A. The SCC should monitor the break condition and wait
for it to terminate. When the break condition stops, the
single NULL character in the receive buffer should be
read and discarded.
Q. Where can you get the DTR input if the DTR/REQ
pin is being used for DMA?
A. The SYNC can be used as an input if operating in the
Async mode. It will cause an interrupt on both transi-
tions.
Q. When a special condition occurs due to a parity
error, will a receive interrupt for that byte still be
generated?
A. No. In the case of Receive interrupt on Special Condi-
tion Only mode, the interrupt will not occur until after
the character with the special condition is read. In the
case of Receive Interrupt on All Characters or Special
Condition Only mode, the interrupt is generated on ev-
ery character whether or not it has a special condition.
SCC™/ESCC™ User’s Manual
Zilog SCC
Q. In the Auto Enable mode, what happens when
CTS/ goes inactive (high) in the middle of transfer-
ring a byte?
A. If the Auto Enable mode is selected, the CTS/ pin is an
enable for the transmitter. So, when CTS/ is inactive,
transmit stops immediately.
Q. Can X1 clock mode really be used for the Async
operation?
A. X1 mode cannot be used unless the receive and trans-
mit clocks are synchronized. Using a synchronous mo-
dem is one way of satisfying this requirement.
Q. When does the FIFO buffer lock on an error
condition?
A. The receive data FIFO gets locked only in cases where
the following receiver interrupt modes are selected:
– Receive Interrupt on Special Condition only
– Receive Interrupt on First Character or Special
Condition
In both of these modes, the Special Condition interrupt
occurs after the character with the special condition
has been read. The error status has to be valid when
read in the service routine. The Special Condition
locks the FIFO and guarantees that the DMA will not
transfer any characters until the Special Condition has
been serviced.
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