Z85233 Datasheet, PDF (19/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
General Description
A//B. Channel A/Channel B (input). This signal selects the /CS0. Chip Select 0 (input, active Low). This signal is
channel in which the read or write operation occurs. High latched concurrently with the addresses on AD7-AD0 and
selects channel A and Low selects channel B.
must be active for the intended bus transaction to occur.
1
D//C. Data/Control Select (input). This signal defines the CS1. Chip Select 1 (input, active High). This second select
type of information transferred to or from the Z85X30. signal must also be active before the intended bus trans-
High means data is being transferred and Low indicates action can occur. CS1 must remain active throughout the
a command.
transaction.
1.4.3 Pin Descriptions, (Z80X30 Only)
AD7-AD0. Address/Data Bus (bidirectional, active High,
tri-state). These multiplexed lines carry register addresses
to the Z80X30 as well as data or control information to and
from the Z80X30.
R//W. Read//Write (input, read active High). This signal
specifies whether the operation to be performed is a read
or a write.
/DS. Data Strobe (input, active Low). This signal provides
timing for the transfer of data into and out of the Z80X30.
If /AS and /DS are both Low, this is interpreted as a reset.
/AS. Address Strobe (input, active Low). Address on AD7-
AD0 are latched by the rising edge of this signal.
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