Z85233 Datasheet, PDF (70/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
SCC/ESCC Ancillary Support Circuitry
Receive
Data
3
DPLL
Output
Correction
Windows ^{+1 -1 +1 -1 +1 -1 +1 -1 +1 -1 +1 -1 +1 -1 +1 -1 +1}
Count
Length ^{32 32}
32
31
31
31
33
33
33
Figure 3-7. DPLL Operating Example (NRZI Mode)
3.4.2 DPLL Operation in the FM Modes
To operate in FM mode, the DPLL must be supplied with a
clock that is 16 times the data rate. The DPLL uses this
clock, along with the receive data, to construct, receive,
and transmit clock outputs that are phased to receive and
transmit data properly.
In FM mode, the counter in the DPLL counts from 0 to 31,
but now each cycle corresponds to 2-bit cells. To make
adjustments to remain in phase with the receive data, the
DPLL divides a pair of bit cells into five regions, making the
adjustment to the counter dependent upon which region the
transition on the receive data input occurred (Figure 3-8).
Bit Cell
Count 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Correction
RX DPLL Out
+1
No Change
Ignored
+1
No Change
TX DPLL Out
Figure 3-8. DPLL Operation in the FM Mode
UM010901-0601
3-9