Z85233 Datasheet, PDF (241/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
Using SCC with Z8000 in SDLC Protocol
SDLC PROTOCOL
Data communications today require a communications
protocol that can transfer data quickly and reliably. One
such protocol, Synchronous Data Link Control (SDLC), is
the link control used by the IBM Systems Network
Architecture (SNA) communications package. SDLC is a
subset of the International Standard Organization (ISO)
link control called High-Level Data Link Control (HDLC),
which is used for international data communications.
SDLC is a bit-oriented protocol (BOP). It differs from byte-
control protocols (BCPs), such as Bisync, in that it uses
only a few bit patterns for control functions instead of
several special character sequences. The attributes of the
SDLC protocol are position dependent rather than
character dependent, so the data link control is determined
by the position of the byte as well as by the bit pattern.
A character in SDLC is sent as an octet, a group of eight
bits. Several octets combine to form a message frame, in
which each octet belongs to a particular field. Each
message contains: opening flag, address, control,
information, Frame Check Sequence (FCS), and closing
flag (Figure 1).
Figure 1. Fields of the SDLC Transmission Frame
Both flag fields contain a unique binary pattern, 0111110,
which indicates the beginning or the end of the message
frame. This pattern simplifies the hardware interface in
receiving devices so that multiple devices connected to a
common link do not conflict with one another. The
receiving devices respond only after a valid flag character
has been detected. Once communication is established
with a particular device, the other devices ignore the
message until the next flag character is detected.
The address field contains one of more octets, which are
used to select a particular station on the data link. An
address of eight 1s is a global address code that selects all
the devices on the data link. When a primary station sends
a frame, the address field is used to select one of several
secondary stations. When a secondary station sends a
message to the primary station, the address field contains
the secondary station address, i.e., the source of the
message.
The control field follows the address field and contains
information about the type of frame being sent. The control
field consists of one octet that is always present.
The information field contains any actual transferred data.
This field may be empty or it may contain an unlimited
number of octets. However, because of the limitations of
the error-checking algorithm used in the frame-check
sequence, however, the maximum recommended block
size is approximately 4096 octets.
The frame check sequence field follows the information or
control field. The FCS is a 16-bit Cyclic Redundancy
Check (CRC) of the bits in the address, control, and
information fields. The FCS is based on the CRC-CCITT
code, which uses the polynomial (x¹⁶ + x¹² + x⁵ + 1). The
Z8030 SCC contains the circuitry necessary to generate
and check the FCS field.
Zero insertion and deletion is a feature of SDLC that allows
any data pattern to be sent. Zero insertion occurs when
five consecutive 1s in the data pattern are transmitted.
After the fifth 1, a 0 is inserted before the next bit is sent.
The extra 0 does not affect the data in any way and is
deleted by the receiver, thus restoring the original data
pattern.
Zero insertion and deletion insures that the data stream
will not contain a flag character or abort sequence. Six 1s
preceded and followed by 0s indicate a flag sequence
character. Seven to fourteen 1s signify and abort; Seven
to fourteen 1s signify an abort; 15 or more 1s indicate an
idle (inactive) line. Under these three conditions, zero
insertion and deletion are inhibited. Figure 2 illustrates the
various line conditions.
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