Z85233 Datasheet, PDF (87/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Data Communication Modes
4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)
In all cases except External Sync mode, the /SYNC pin is
an output that is driven Low by the SCC to signal that a
sync character has been received. The /SYNC pin is
activated regardless of character boundaries, so any
external circuitry using it should only respond to the /SYNC
pulse that occurs while the receiver is in Hunt mode. The
timing for the /SYNC signal is shown in Figure 4-7.
/RTxC
PCLK
/SYNC
Figure 4-7. /SYNC as an Output
State Changes in One
/RTxC Clock Cycle
To prevent sync characters from entering the receive data
FIFO, set the Sync Character Load Inhibit bit (D1) in WR3
to 1. While this bit is set to 1, characters about to be loaded
into the receive data FIFO are compared with the contents
of WR6. If all eight bits match the character, it is not loaded
into the receive data FIFO. Because the comparison is
across eight bits, this function should only be used with 8-
bit sync characters. It cannot be used with 12- or 16-bit
sync characters. Both leading sync characters are re-
moved in the case of a 6-bit sync character. Care must be
exercised in using this feature because sync characters
which are not transferred to the receive data FIFO will au-
tomatically be excluded from CRC calculation. This works
properly only in the 8-bit case.
The number of bits per character is controlled by bits D7
and D6 of WR3. Five, six, seven, or eight bits per character
may be selected via these two bits. The data is right-justi-
fied in the receive data buffer. The SCC merely takes a
snapshot of the receive data stream at the appropriate
times, so the “unused” bits in the receive buffer are only
the bits following the character in the data stream.
An additional bit carrying parity information is selected by
setting bit D0 of WR4 to 1. Note that this also enables par-
ity for the transmitter. The bit D1 of WR4 selects parity
sense. If this bit is set to 1, the received character is
checked for even parity. If WR4 D1 is reset to 0, the re-
ceived character is checked for odd parity. The additional
bit per character is transferred to the FIFO as a part of data
when the data plus parity is less than 8 bits per character.
The Parity Error bit in the receive error FIFO may be pro-
grammed to cause a Special Receive Condition interrupt
by setting bit D2 of WR1 to 1. Once set, this error bit is
latched and remains active until an Error Reset command
has been issued. If interrupts are not used to transfer data,
the Parity Error, CRC Error, and Overrun Error bits in RR1
should be checked before the data is removed from the re-
ceive data FIFO.
The character length can be changed at any time before
the new number of bits has been assembled by the
receiver, but, care should be exercised as unexpected
results may occur. A representative example would be
switching from five bits to eight bits and back to five bits
(Figure 4-8).
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