Z85233 Datasheet, PDF (37/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.4 INTERFACE PROGRAMMING (Continued)
2.4.4.1 Master Interrupt Enable Bit
The Master Interrupt Enable (MIE) bit, WR9 D3, must be
set to enable the SCC to generate interrupts. The MIE bit
should be set after initializing the SCC registers and en-
abling the individual interrupt enables. The SCC requests
an interrupt by asserting the /INT pin Low from its open-
drain state only upon detection that one of the enabled in-
terrupt conditions has been detected.
2.4.4.2 Interrupt Enable Bit
The Interrupt Enable (IE) bits control interrupt requests
from each interrupt source on the SCC. If the IE bit is set
to 1 for an interrupt source, that source may generate an
interrupt request, providing all of the necessary conditions
are met. If the IE bit is reset, no interrupt request is gener-
ated by that source. The transmit interrupt IE bit is WR1
D1. The receive interrupt IE bits are WR1 D3 and D4. The
external status interrupts are individually enabled in WR15
with the master external status interrupt enable in WR1
D0. Reminder: The MIE bit, WR9 D3, must be set for any
interrupt to occur.
2.4.4.3 Interrupt Pending Bit
The Interrupt Pending (IP) bit for a given source of interrupt
is set by the presence of an interrupt condition in the SCC.
It is reset directly by the processor, or indirectly by some
action that the processor may take. If the corresponding IE
bit is not set, the IP for that source of interrupt will never be
set. The IP bits in the SCC are read only via RR3 as shown
in Figure 2-12.
Read Register 3
D7 D6 D5 D4 D3 D2 D1 D0
* Always 0 In B Channel
Channel B Ext/Stat
Channel B Tx IP
Channel B Rx IP
Channel A Ext/Stat
Channel A Tx IP
Channel A Rx IP
0
0
2.4.4.4 Interrupt-Under-Service Bit
The Interrupt-Under-Service (IUS) bits are completely hid-
den from the processor. An IUS bit is set during an inter-
rupt acknowledge cycle for the highest priority IP. On the
CMOS or ESCC, the IUS bits can be set by either a hard-
ware acknowledge cycle with the /INTACK pin or through
software if WR9 D5=1 and then reading RR2.
The IUS bits control the operation of internal and external
daisy-chain interrupts. The internal daisy chain links the
six sources of interrupt in a fixed order, chaining the IUS
bit of each source. If an internal IUS bit is set, all lower pri-
ority interrupt requests are masked off; during an interrupt
acknowledge cycle the IP bits are also gated into the daisy
chain. This ensures that the highest priority IP selected
has its IUS bit set. At the end of an interrupt service rou-
tine, the processor must issue a Reset Highest IUS com-
mand in WR0 to re-enable lower priority interrupts. This is
the only way, short of a software or hardware reset, that an
IUS bit may be reset.
Note: It is not necessary to issue the Reset Highest IUS
command in the interrupt service routine, since the IUS
bits can only be set by an interrupt acknowledge if no hard-
ware acknowledge or software acknowledge cycle (not
with NMOS) is executed. The only exception is when the
SDLC Frame Status FIFO (not with NMOS) is enabled and
“receive interrupt on special condition only” is used. See
section 4.4.3 for more details on this mode.
2.4.4.5 Disable Lower Chain Bit
The Disable Lower Chain (DLC) bit in WR9 (D2) is used to
disable all peripherals in a lower position on the external
daisy chain. If WR9 D2=1, the IEO pin is driven Low and
prevents lower priority devices from generating an inter-
rupt request. Note that the IUS bit, when set, will have the
same effect, but is not controllable through software.
Figure 2-12. RR3 Interrupt Pending Bits
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