Z85233 Datasheet, PDF (242/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
Using SCC with Z8000 in SDLC Protocol
1
Figure 2. Bit Patterns for Various Line Conditions
The SDLC protocol differs from other synchronous
protocols with respect to frame timing. In Bisync mode, for
example, a host computer might temporarily interrupt
transmission by sending sync characters instead of data.
This suspended condition continues as long as the
receiver does not time out. With SDLC, however, it is
invalid to send flags in the middle of a frame to idle the line.
Such action causes an error condition and disrupts orderly
operation. Thus, the transmitting device must send a
complete frame without interruption. If a message cannot
be transmitted completely, the primary station sends an
abort sequence and restarts the message transmission at
a later time.
SYSTEM INTERFACE
The Z8002 Development Module consists of a Z8002
CPU, 16K words of dynamic RAM, 2K words of EPROM
monitor, a Z80A SIO providing dual serial ports, a
counter/timer channels, two Z80A PIO devices providing
32 programmable I/O lines, and wire wrap area for
prototyping. The block diagram is depicted in Figure 3.
Each of the peripherals in the development module is
connected in a prioritized daisy chain configuration. The
SCC is included in this configuration. The SCC is included
in this configuration by tying its IEI line to the IEO line of
another device, thus making it one step lower in interrupt
priority compared to the other device.
UM010901-0601
Figure 3. Block Diagram of Z8000 DM
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