Z85233 Datasheet, PDF (256/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
Boost Your System Performance Using The Zilog ESCC^™
TRANSMIT FIFO INTERRUPT
In the ESCC, transmit interrupt frequencies are reduced by If WR7' D5 is set, the transmit buffer empty interrupt is
1 ^{a deeper Transmit FIFO and the revised transmit interrupt generated when the transmit FIFO is completely empty.}
structure. If the WR7' D5 Transmit FIFO Interrupt Level bit Enabling the transmit FIFO interrupt level, together with
is reset, the transmit interrupt is generated when the entry polling the Transmit Buffer Empty (TBE) bit in RR0, causes
location of the FIFO is empty, i.e., more data can be significant transmit interrupt frequency reduction. Transmit
written. This is downward compatible with a SCC Transmit data is sent in blocks of four bytes (algorithm is illustrated
Interrupt since the SCC only has a one-byte transmit buffer in Figure 4). This helps to offload those systems which
instead of a four-byte Transmit FIFO.
have long interrupt latency or a fully loaded Operating
System.
TX FIFO Int.
Level Enabled
TBE Interrupt
Service
NO
Transmit FIFO
Full
RR0
TBE = '1'?
YES
Write Data To
Transmit FIFO
Transmit FIFO
Is Loaded
With Data
Figure 4. Flowchart of Transmit Interrupt Service Routine to Reduce Transmit Interrupt Frequencies
UM010901-0601
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