Z85233 Datasheet, PDF (132/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Register Descriptions
Read Register 2
D7 D6 D5 D4 D3 D2 D1 D0
* Modified In B Channel
V0
V1
V2
V3
Interrupt
V4
Vector *
V5
V6
V7
5.3.6 Read Register 5 (ESCC and 85C30 Only)
On the ESCC, Read Register 5 reflects the contents of
5 ^{Write Register 5 provided the Extended Read option is en-}
abled. Otherwise, this register returns an image of RR1.
On the NMOS/CMOS version, a read to this register re-
turns an image of RR1.
5.3.7 Read Register 6 (Not on NMOS)
On the CMOS and ESCC, Read Register 6 contains the
least significant byte of the frame byte count that is current-
ly at the top of the Status FIFO. RR6 is shown in Figure 5-
23. This register is readable only if the FIFO is enabled (re-
fer to the description Write Register 15, bit D2 and Section
4.4.3). Otherwise, this register is an image of RR2.
Figure 5-21. Read Register 2
5.3.4 Read Register 3
RR3 is the interrupt Pending register. The status of each
of the interrupt Pending bits in the SCC is reported in this
register. This register exists only in Channel A. If this
register is accessed in Channel B, all 0s are returned. The
two unused bits are always returned as 0. Figure 5-22
shows the bit positions for RR3.
Read Register 3
D7 D6 D5 D4 D3 D2 D1 D0
* Always 0 In B Channel
Channel B Ext/Status IP
Channel B Tx IP
Channel B Rx IP
*
Channel A Ext/Status IP
Channel A Tx IP
Channel A Rx IP
0
0
Figure 5-22. Read Register 3
5.3.5 Read Register 4 (ESCC and 85C30 Only)
On the ESCC, Read Register 4 reflects the contents of
Write Register 4 provided the Extended Read option is en-
abled. Otherwise, this register returns an image of RR0.
On the NMOS/CMOS version, a read to this location re-
turns an image of RR0.
On the NMOS version, a read to this register location re-
turns an image of RR2.
5.3.8 Read Register 7 (Not on NMOS)
On the CMOS and ESCC, Read Register 7 contains the
most significant six bits of the frame byte count that is
currently at the top of the Status FIFO. Bit D7 is the FIFO
Overflow Status and bit D6 is the FIFO Data Available
Status. The status indications are given in Table 5-13. RR7
is shown in Figure 5-24. This register is readable only if the
FIFO is enabled (refer to the description Write Register 15,
bit D2). Otherwise this register is an image of RR3. Note,
for proper operation of the FIFO and byte count logic, the
registers should be read in the following order: RR7, RR6,
RR1.
Read Register 6 *
D7 D6 D5 D4 D3 D2 D1 D0
BC0
BC1
BC2
BC3
BC4
BC5
BC6
BC7
* Can only be accessed if the SDLC FIFO enhancement
is enabled (WR15 bit D2 set to 1)
SDLC FIFO Status and Byte Count (LSB)
Figure 5-23. Read Register 6 (Not on NMOS)
UM010901-0601
5-25