Z85233 Datasheet, PDF (110/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Write Register 0 (non-multiplexed bus mode)
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 Register 0
0 0 1 Register 1
0 1 0 Register 2
0 1 1 Register 3
1 0 0 Register 4
1 0 1 Register 5
1 1 0 Register 6
1 1 1 Register 7
0 0 0 Register 8
0 0 1 Register 9
0 1 0 Register 10
0 1 1 Register 11
1 0 0 Register 12
*
1 0 1 Register 13
1 1 0 Register 14
1 1 1 Register 15
0 0 0 Null Code
0 0 1 Point High
0 1 0 Reset Ext/Status Interrupts
0 1 1 Send Abort (SDLC)
1 0 0 Enable Int on Next Rx Character
1 0 1 Reset Tx Int Pending
1 1 0 Error Reset
1 1 1 Reset Highest IUS
0 0 Null Code
0 1 Reset Rx CRC Checker
1 0 Reset Tx CRC Generator
1 1 Reset Tx Underrun/EOM Latch
* ^{With Point High Command}
Figure 5-1. Write Register 0 in the Z85X30
Write Register 0 (multiplexed bus mode)
D7 D6 D5 D4 D3 D2 D1 D0
0 0 ^{Null Code}
0 1 Null Code
1 0 Select Shift Left Mode
1 1 Select Shift Right Mode ^*
0
0 0 0 Null Code
0 0 1 Null Code
0 1 0 Reset Ext/Status Interrupts
0 1 1 Send Abort
1 0 0 Enable Int on Next Rx Character
1 0 1 Reset Tx Int Pending
1 1 0 Error Reset
1 1 1 Reset Highest IUS
0 0 Null Code
0 1 Reset Rx CRC Checker
1 0 Reset Tx CRC Generator
1 1 Reset Tx Underrun/EOM Latch
* B Channel Only
Figure 5-2. Write Register 0 in the Z80X30
SCC™/ESCC™ User’s Manual
Register Descriptions
At the start of the CRC transmission, the Tx Under-
run/EOM latch is set. The Reset command can be issued
5 ^{at any time during a message. If the transmitter is disabled,}
this command does not reset the latch. However, if no Ex-
ternal Status interrupt is pending, or if a Reset External
Status interrupt command accompanies this command
while the transmitter is disabled, an External/Status inter-
rupt is generated with the Tx Underrun/EOM bit reset in
RR0.
Bits D5-D3: Command Codes for the SCC.
Null Command (000). The Null command has no effect on
the SCC.
Point High Command (001). This command effectively
adds eight to the Register Pointer (D2-D0) by allowing
WR8 through WR15 to be accessed. The Point High com-
mand and the Register Pointer bits are written simulta-
neously. This command is used in the Z85X30 version of
the SCC. Note that WR0 changes form depending upon
the SCC version. Register access for the Z80X30 version
of the SCC is accomplished through direct addressing.
Reset External/Status Interrupts Command (010). After
an External/Status interrupt (a change on a modem line or
a break condition, for example), the status bits in RR0 are
latched. This command re-enables the bits and allows in-
terrupts to occur again as a result of a status change.
Latching the status bits captures short pulses until the
CPU has time to read the change.
The SCC contains simple queueing logic associated with
most of the external status bits in RR0. If another Exter-
nal/Status condition changes while a previous condition is
still pending (Reset External/Status Interrupt has not yet
been issued) and this condition persists until after the com-
mand is issued, this second change causes another Exter-
nal/Status interrupt. However, if this second status change
does not persist (there are two transitions), another inter-
rupt is not generated. Exceptions to this rule are detailed
in the RR0 description.
Send Abort Command (011). This command is used in
SDLC mode to transmit a sequence of eight to thirteen 1s.
This command always empties the transmit buffer and
sets Tx Underrun/EOM bit in Read Register 0.
Enable Interrupt On Next Rx Character Command
(100). If the interrupt on First Received Character mode is
selected, this command is used to reactivate that mode af-
ter each message is received. The next character to enter
the Receive FIFO causes a Receive interrupt. Alternative-
ly, the first previously stored character in the FIFO causes
a Receive interrupt.
UM010901-0601
5-3