Z85233 Datasheet, PDF (109/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Register Descriptions
5.1 INTRODUCTION (Continued)
Among these registers, WR9 (Master Interrupt Control and
Reset register) can be accessed through either channel.
The RR2 (Interrupt Vector register) returns the interrupt
vector modified by status, if read from Channel B, and writ-
ten value (without modification), if read from Channel A.
Channel A has an additional read register which contains
all the Interrupt Pending bits (RR3A).
Write Registers. Eleven write registers are used for con-
trol (includes transmit buffer/FIFO); two for sync character
generation/detection; two for baud rate generation. In ad-
dition, there are two write registers which are shared by
both channels; one is the interrupt vector register (WR2);
the other is the Master Interrupt and Reset register (WR9).
On the ESCC and 85C30, there is one additional register
(WR7') to control enhanced features.
See Table 5-1 for a summary of Write registers.
Read Registers. Four read registers indicate status infor-
mation; two are for baud rate generation; one for the re-
ceive buffer. In addition, there are two read registers which
are shared by both channels; one for the interrupt pending
bits; another for the interrupt vector. On the CMOS/ESCC,
there are two additional registers, RR6 and RR7. They are
available if the Frame Status FIFO feature was enabled in
the SDLC mode of operation. On the ESCC, there is an
“extended read” option and if its enabled, certain write reg-
isters can be read back.
See Table 5-2 for a summary of Read registers.
5.2 WRITE REGISTERS
The SCC write register set in each channel has 11 control
registers (includes transmit buffer/FIFO), two sync charac-
ter registers, and two baud rate time constant registers.
The interrupt control register and the master interrupt con-
trol and reset register are shared by both channels. In ad-
dition to these, the ESCC and 85C30 has a register (WR7';
prime 7) to control the enhancements.
Between 80X30 and 85X30, the variation in register defini-
tion is a command decode structure; Write Register 0
(WR0). The following sections describe in detail each write
register and the associated bit configuration for each.
The following sections describe WR registers in detail:
5.2.1 Write Register 0 (Command Register)
WR0 is the command register and the CRC reset code
register. WR0 takes on slightly different forms depending
upon whether the SCC is in the Z85X30 or the Z80X30.
Figure 5-1 shows the bit configuration for the Z85X30 and
includes register select bits in addition to command and re-
set codes.
Figure 5-2 shows the bit configuration for the Z80X30 and
includes (in Channel B only) the address decoding select
described later.
The following bit description for WR0 is identical for both
versions except where specified:
Bits D7 and D6: CRC Reset Codes 1 And 0.
Null Command (00). This command has no effect on the
SCC and is used when a write to WR0 is necessary for
some reason other than a CRC Reset command.
Reset Receive CRC Checker Command (01). This com-
mand is used to initialize the receive CRC circuitry. It is
necessary in synchronous modes (except SDLC) if the En-
ter Hunt Mode command in Write Register 3 is not issued
between received messages. Any action that disables the
receiver initializes the CRC circuitry. Resetting the Re-
ceive CRC Checker command is accomplished automati-
cally in SDLC mode.
Reset Transmit CRC Generator Command (10). This
command initializes the CRC generator. It is usually is-
sued in the initialization routine and after the CRC has
been transmitted. A Channel Reset does not initialize the
generator and this command is not issued until after the
transmitter has been enabled in the initialization routine.
On the ESCC and 85C30, this command is not needed if
Auto EOM Reset mode is enabled (WR7' D1=1).
Reset Transmit Underrun/EOM Latch Command (11).
This command controls the transmission of CRC at the
end of transmission (EOM). If this latch has been reset,
and a transmit underrun occurs, the SCC automatically
appends CRC to the message. In SDLC mode with Abort
on Underrun selected, the SCC sends an abort and Flag
on underrun if the TX Underrun/EOM latch has been reset.
5-2
UM010901-0601