Z85233 Datasheet, PDF (13/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
General Description
The Z85C30 CMOS SCC has added new features, while ESCC (Enhanced SCC) is pin and software compati-
maintaining 100% hardware/software compatibility. It has ble to the CMOS version, with the following additional
the following new features:
enhancements.
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s New programmable WR7' (write register 7 prime) to s Deeper transmit FIFO (4 bytes)
enable new features.
s Deeper receive FIFO (8 bytes)
s Improvements to support SDLC mode of synchronous
communication:
s Programmable FIFO interrupt and DMA request level
– Improved functionality to ease sending back-to
back frames
– Automatic SDLC opening Flag transmission*
– Automatic Tx Underrun/EOM Latch reset in SDLC
mode*
– Automatic /RTS deactivation*
– TxD pin forced “H” in SDLC NRZI mode after
closing flag*
– Complete CRC reception*
– Improved response to Abort sequence in status
FIFO
– Automatic Tx CRC generator preset/reset
– Extended read for write registers*
– Write data setup timing improvement
s Seven enhancements to improve SDLC link layer
supports:
– Automatic transmission of the opening flag
– Automatic reset of Tx Underrun/EOM latch
– Deactivation of /RTS pin after closing flag
– Automatic CRC generator preset
– Complete CRC reception
– TxD pin automatically forced high with NRZI
encoding when using mark idle
– Status FIFO handles better frames with an
ABORT
– Receive FIFO automatically unlocked for special
receive interrupts when using the SDLC status
FIFO
s Improved AC timing:
– Three to 3.5 PCLK access recovery time.
– Programmable /DTR//REQ timing*
– Elimination of write data to falling edge of /WR
setup time requirement
– Reduced /INT timing
s Delayed bus latching for easier microprocessor
interface
s New programmable features added with Write Register
7' (WR seven prime)
s Write registers 3, 4, 5 and 10 are now readable
s Other features include:
– Extended read function to read back the written
value to the write registers*
– Latching RR0 during read
– RR0, bit D7 and RR10, bit D6 now has reset
defaultvalue.
Some of the features listed above are available by de-
fault, and some of them (features with “*”) are disabled on
default.
s Read register 0 latched during access
s DPLL counter output available as jitter-free transmitter
clock source
s Enhanced /DTR, /RTS deactivation timing
UM010901-0601
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