Z85233 Datasheet, PDF (163/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
The Z180™ Interfaced with the SCC at MHZ
EPROM INTERFACE
During an Opcode fetch cycle, data sampling of the bus is
on the rising PHI clock edge of T3 and on the falling edge
of T3 during a memory read cycle. Opcode fetch cycle data
sample timing is half a clock cycle earlier. Table 2 shows
how a memory read cycles’ timing requirements are easier
than an opcode fetch cycle by half a PHI cycle time. If the
timing requirements for an Opcode fetch cycle meet
specifications, the design satisfies the timing requirements
for a memory read cycle.
Table 2 has some equations for an opcode fetch, memory
read/write cycle.
Table 2. Parameter Equations (10 MHz) Opcode Fetch/Memory Read/Write Cycle
Parameters
Address Valid to Data Valid (Opcode Fetch)
Address Valid to Data Valid (Memory Read
/MREQ Active to Data Valid (Opcode Fetch)
/MREQ Active to Data Valid (Memory Read)
/RD Active to Data Valid (Opcode Fetch)
/RD Active to Data Valid (Memory Read)
Memory Write Cycle /WR Pulse Width
Note: * w is the number of wait states.
Z180 Equation
2(1+w)tcyc-tAD-tDRS
2(1+w)tcyc+tCHW+tcf-tAD-tDRS
(1+w)tcyc+tCLW-tMED1-tDRS
(2+w)tcyc-tMED1-tDRS
(1+w)tcyc+tCLW-tRRD1-tDRS
(2+w)tcyc-tRRD1-tDRS
tWRP+w*tcyc
Value
105+100w min
155+100w min
55+100w min
105+100w min
55+100w min
105+100w min
110+100w min
Units
ns
ns
ns
ns
ns
ns
ns
The propagation delay for the decoded address and gates
in the previous calculation is zero. Hence, on the real
design, subtracting another 20-30 ns to pay for
propagation delays, is possible. The 27C256 provides the
EPROM for this board. Typical timing parameters for the
27C256 are in Table 3.
Table 3. EPROM (27C256) Key Timing Parameters
(Values May Vary Depending On Mfg.)
Access Time
170 ns 200 ns 250 ns
Parameter
Max Max Max
Addr Access Time
170 200 250
/E to Data Valid
170 200 250
/OE to Data Valid
75 75 100
Note: Table 3 shows “Access Time” as applying /E to data valid.
“/OE active to data valid” is shorter than “address access time”.
Hence, the interface logic for the EPROM is: Realize a 170 ns or
faster EPROM access time by adding one wait state (using the
on-chip wait state generator of the Z180). A 200 ns requirement
uses two wait states for memory access.
SRAM Interface
Table 4 has timing parameters for 256K bit SRAM for this
design.)
Table 4. 256K SRAM Key Timing parameters
(Values May Vary Depending On Mfg.)
Parameter
Read Cycle:
/E to Data Valid
/G to Data Valid
Access Time
85 ns 100 ns 150 ns
Min Min Min
85 100 150
45 40 60
Write Cycle:
Write Cycle Time
Addr Valid to End of Write
Chip Select to End of Write
Data Select to End of Write
Write Pulse Width
Addr Setup Time
85 100 150
75 80 100
75 80 100
40 40 60
60 60 90
0
0
0
SRAM Read Cycle. An SRAM read cycle shares the
same considerations as an EPROM interface.
Like EPROM, SRAMs’ “access time” applies /G to data
valid, and “/E active to data valid” is shorter than “access
time.” This design allows the use of a 150 ns access time
SRAM by adding one wait state (using the on-chip wait
state generator of the Z180). The circuit is common to the
EPROM memory read cycle.
No wait states are necessary if there is a 85 ns, or faster,
access time by using SRAMs. Since the Z180 has on-chip
MMU with 85 ns or faster SRAM just copy the contents of
EPROM (application program starts at logical address
0000h) into SRAM after power on. Set up the MMU to
SRAM area to override the EPROM area and stop
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