Z85233 Datasheet, PDF (103/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Data Communication Modes
4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)
Frame Status FIFO Circuitr
SCC Status Reg
RR1 Residue Bits(3)
Overrun, CRC Error
Byte Counter
5 Bits
14 Bits
FIFO Array
10 Deep by 19 Bits Wide
Reset on Flag Detect
Increment on Byte DET
Enable Count in SDLC
End of Frame Signal
Status Read Comp
Tail Pointer
4-Bit Counter
Head Pointer
4-Bit Counter
5 Bits
EOF = 1
6 Bits 8 Bits
4-Bit Comparator
Over
Equal
6-Bit MUX
EN
2 Bits
Interface
to SCC
6 Bits Bit 7 Bit 6 Bits 5-0 RR6
RR1
FIFO Enable
RR7 D5-D0 + RR6 D7 - D0
Byte Counter Contains 14 bits
for a 16 KByte maximum count.
WR(15) Bit 2
Set Enables
Status FIFO
RR7 D6
FIFO Data available status bit Status Bit set to 1
When reading from FIFO.
RR7 D7
FIFO Overflow Status Bit
MSB pf RR(7) is set on Status FIFO overflow
In SDLC Mode the following definitions apply.
- All Sent bypasses MUX and equals contents of SCC Status Register.
- Parity Bits bypasses MUX and does the same.
- EOF is set to 1 whenever reading from the FIFO.
Figure 4-15. SDLC Frame Status FIFO (N/A on NMOS)
4-28
UM010901-0601