Z85233 Datasheet, PDF (310/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Zilog SCC
Q. Does Valid Access Recovery Time affect the inter-
rupt acknowledge cycle?
A. No. The interrupt vector is put on the bus by the SCC
during the interrupt acknowledge cycle, but does not
require any recovery time.
Q. Why can some systems violate the recovery time
by 1 or 2 PCLK’s without affecting the data to the
SCC?
A. This violation may or may not matter to the SCC. This
phase relationship between PCLK, /RD, /WR, (/AS,
/DS for Z8030) can by ASYNC. The SCC requires
some time internally to synchronize these signals. The
electrical specs for the SCC indicate a recovery time,
which is the worst case maximum.
INTERRUPT CONSIDERATIONS
Q. What conditions must exist for the SCC to gener-
ate an interrupt request?
A. Interrupts must be enabled (MIE = 1 and IE = 1). The
Interrupt Enable Input (IEI) must be high. The interrupt
pending bit (IP) must be set and its interrupt under ser-
vice bit (IUS) must be reset. No interrupt acknowledge
cycle may be active.
Q. How can the /INTACK signal be synchronized with
PCLK?
A. /INTACK needs to be synchronized with PCLK. This
can be accomplished by changing /INTACK only on
the falling edge of PCLK by using a D flip-flop that is
clocked with the inverted PCLK.
Q. Is /CE required during an Interrupt Acknowledge
cycle?
A. No.
Q. How long does /INT stay active low when request-
ing an interrupt?
A. If the SCC is operated in a polled mode, the /INT will
remain active until the IP bit is reset. For an interrupt
acknowledge cycle, the /INT will go inactive shortly af-
ter the falling edge of /RD or /DS when the IUS bit is
set.
Q. Can you use the SCC without a hardware interrupt
acknowledge?
A. Yes. If you are not using the hardware daisy chain, you
don’t need to give an interrupt acknowledge. Tie the
intack pin high, enable interrupts, and on responding
to an interrupt, check RR3 for the cause, and special
receive conditions if you are in receive mode. The in-
ternal daisy-chain settling time must still be met. (IEI to
IEO delay time specification.)
Q. How do you acknowledge an interrupt without a
hardware interrupt acknowledge?
A. Reset the responsible interrupt pending bit (IP). The
/INT line follows the IP bit.
Q. When are the IP bits cleared?
A. A transmitter empty IP is cleared by writing to the
data register. A receive character available IP is
cleared by reading the data register. The exter-
nal/status interrupt IP is cleared by the command Re-
set Ext/Status Interrupts.
Q. Can the IP bits be set while the SCC is servicing
other interrupts?
A. Yes. If the interrupting condition has a higher priority
than the interrupt currently being serviced, it causes
another interrupt, thus nesting the interrupt services.
Q. Can the IUS bits be accessed?
A. No. They are not accessible.
Q. When do IUS bits get set?
A. The IUS bits are set during an interrupt acknowledge
cycle on the falling edge or /RD or /DS.
Q. How do you reset interrupts on the SCC?
A. The interrupt under service bit (IUS) can be reset by
the command “Reset Highest IUS” or 38 Hex to WR0.
Reset Highest IUS should be the last command issued
in the interrupt service routine.
Q. Why is the interrupt daisy chain settle time re-
quired?
A. This mechanism allows the peripheral with the highest
priority interrupt pending in the hardware interrupt dai-
sy chain to have its interrupt serviced.
Q. Is there still a settle time if the peripherals are not
chained?
A. Even if only one SCC is used, there still is a minimum
daisy-chain settle time due to the internal chain.
Q. How should the vectors be read when utilizing the
/INTACK?
A. /INTACK should be tied to 5 volts through a register.
Erroneous reads can result from a floating INTACK.
The interrupt vectors can be read after an interrupt
from RR2.
Q. How is the vector register different from the other
registers?
A. The vector register is shared between both channels.
The Write register can be accessed from either chan-
nel. Reading “Read Register 2” on Channel A (RR2A)
returns the unmodified vector, and RR2B returns the
UM010901-0601
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