Z85233 Datasheet, PDF (239/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
Serial Communication Controller (SCC^™): SDLC Mode of Operation
THE SDLC LOOP MODE (Continued)
Notes on Figure 6:
1. The master SCC sends EOP by switching from flag on
idle to mark on idle
2. At initialization, all Slave stations were set up for SDLC
loop mode At this point, the Slave station connects its
RxD pin to TxD pin with gate propagation delay, and
starts to monitor Rx data for the EOP sequence.
3. On receiving the EOP, the slave generates an
External/Status Interrupt with Break/Abort bit set. A
one bit time delay is inserted between RxD and TxD.
(The GAOP,Go active on Poll, bit should be reset at
this point to avoid unexpected loop entry by the Slave
transmitter.) The Slave’s on-loop bit is set and the
receiver is in hunt mode.
4. Note that there is a one bit time delay between
received data and transmitted data.
5. When the Slave wants to transmit it must first receive
an EOP and have GAOP set.
6. On receiving an EOP, the Slave interrupts with
Break/Abort clear. The EOP is converted to a flag, the
loop sending bit is set, and the transmitter will send
flags until data is written into the Transmit Buffer.
7. Note that the flags overlap.
8. When the slave has sent all of its data the GAOP flag
should be cleared so that the CRC is sent on
underrun.
9. When the closing flag has been sent the Slave reverts
to a one bit delay, which produces another EOP.
10. The master must keep its output marking until its
receiver has received all frames sent by secondaries.
CMOS SCC AND ESCC
The discussion above applies to the NMOS SCC and the
CMOS SCC without the SDLC Frame Status FIFO feature.
The CMOS version and the ESCC have a SDLC Frame
Status FIFO for easier handling of the SDLC mode of
operation. The SDLC Status FIFO is designed for DMA
controlled SDLC receive for high speed SDLC data
transmission, or for systems whose CPU interrupt
processing is not fast.
This FIFO is able to store up to 10 packets’ worth of byte
count (14-bit count) and status information
(Overrun/Parity/CRC error status). To use this feature,
simply enable this FIFO and let DMA transfer data to
memory. While DMA is transferring received data to the
memory, the CPU will check the FIFO and locate the data
in memory, as well as the status information of the
received packet.
Other ESCC enhancements make it easier to handle the
SDLC mode of operation. These include:
s Deeper FIFO (4 Bytes Transmit, and 8 Bytes receive)
s Automatic Opening Flag transmission
s Automatic EOM reset
s Automatic /RTS deactivation
s Fast /DTR//REQ mode
s Complete CRC reception
s Receive FIFO Antilock feature
s Programmable DMA and interrupt request level
s Improved data setup time specification
For more details on these functions, please refer to the
SCC/ESCC Technical manual and related documents.
CONCLUSION
This application note describes the basic operation of the
SCC in SDLC operational modes. With minor variations,
most of these operations also apply to the CMOS SCC
with Status FIFO enabled and the ESCC.
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