Z85233 Datasheet, PDF (246/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
Using SCC with Z8000 in SDLC Protocol
TRANSMIT OPERATION
To transmit a block of data, the main program calls up the The CRC generator is reset and the Transmit CRC bit is
1 ^{transmit data routine. With this routine, each message enabled before the first character is sent, thus including all}
block to be transmitted is stored in memory, beginning with the characters sent to the SCC in the CRC calculation.
location “TBUF” The number of characters contained in
each block is determined by the value assigned to the ^{The SCC transmit underrun/EOM latch must be reset}
“COUNT” parameter in the main module.
sometime after the first character is transmitted by writing
a Reset Tx Underrun/EOM command to WR0. When this
To prepare for transmission, the routine enables the latch is reset, the SCC automatically appends the CRC
transmitter and selects the Wait On Transmit function; it characters to the end of the message in the case of an
then enables the wait function. The Wait on Transmit underrun condition.
function indicates to the CPU whether or not the SCC is
ready to accept data from the CPU. If the CPU attempts to ^{Finally, a three-character delay is introduced at the end of}
send data to the SCC when the transmit buffer is full, the ^{the transmission, which allows the SCC sufficient time to}
SCC asserts its /WAIT line and keeps it Low until the buffer ^{transmit the last data byte and two CRC characters before}
is empty. In response, the CPU extends its I/O cycles until ^{disabling the transmitter.}
the /WAIT line goes inactive, indicating that the SCC is
ready to receive data.
RECEIVE OPERATION
Once the SCC is initialized, it can be prepared to receive
the message. First, the receiver is enabled, placing the
SCC in Hunt mode and thus setting the Sync/Hunt bit in
status register RR0 to 1. In Hunt mode, the receiver
searches the incoming data stream for flag characters.
Ordinarily, the receiver transfers all the data received
between flags to the receive data FIFO. If the receiver is in
Hunt mode, however, no data transfer takes place until an
opening flag is received. If an abort sequence is received,
the receiver automatically re-enters Hunt mode. The Hunt
status of the receiver is reported by the Sync/Hunt bit in
RR0.
The second byte of an SDLC frame is assumed by the
SCC to be the address of the secondary stations for which
the frame is intended. The SCC provides several options
for handling this address. If the Address Search Mode bit
D2 in WR3 is set to zero, the address recognition logic is
disabled and all the received data bytes are transferred to
the receive data FIFO. In this mode, software must
perform any address recognition. If the Address Search
Mode bit is set to one, only those frames with addresses
that match the address programmed in WR6 or the global
address (all 1s) will be transferred to the receive data
FIFO. If the Sync Character Load Inhibit bit (D1) in WR3 is
set to zero, the address comparison is made across all
eight bits of WR6. The comparison can be modified so that
only the four most significant bits of WR6 need match the
received address. This alterations made by setting the
Sync Character Load Inhibit bit to one. In this mode, the
address field is still eight bits wide and is transferred to the
FIFO in the same manner as the data. In this application,
the address search is performed.
When the address match is accomplished, the receiver
leaves the Hunt mode and establishes the Receive
Interrupt on First Character mode. Upon detection of the
receive interrupt, the CPU generates an Interrupt
Acknowledge Cycle. The SCC returns the programmed
vector %2C. This vector points to the location %4472 in the
Program Status Area which contains the receive interrupt
service routine address.
The receive data routine is called from within the receive
interrupt service routine. While expecting a block of data,
the Wait on Receive function is enabled. Receive read
buffer RR8 is read and the characters are stored in
memory location RBUF. The SCC in SDLC mode
automatically enables the CRC checker for all data
between opening and closing flags and ignores the
Receive CRC Enable bit (D3) in WR3. The result of the
CRC calculation for the entire frame in RR1 becomes valid
only when the End of Frame bit is set in RR1. The
processor does not use the CRC bytes, because the last
two bits of the CRC are never transferred to the receive
data FIFO and are not recoverable.
When the SCC recognizes the closing flag, the contents of
the Receive Shift register are transferred to the receive
data FIFO, the Residue Code (not applicable in this
application) is latched, the CRC error bit is latched in the
status FIFO, and the End of Frame bit is set in the receive
status FIFO, a special receive condition interrupt occurs.
The special receive condition register RR1 is read to
determine the bit is zero, the frame received is assumed to
be correct; if the bit is 1, an error in the transmission is
indicated.
Before leaving the interrupt service routine, Reset Highest
IUS (Interrupt Under Service), Enable Interrupt on Next
Receive Character, and Enter Hunt Mode commands are
issued to the SCC.
UM010901-0601
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