Z85233 Datasheet, PDF (185/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
The Z180™ Interfaced with the SCC at MHZ
(Continued)
bcr1l:
bcr1h:
dstat:
dmode:
dcntl:
Table 13. Program Example – Z180 CPU Macro Instructions (Continued)
equ
2eh
equ
2fh
equ
30h
equ
31h
equ
32h
; DMA Byte Count Reg Ch1-low
; DMA Byte Count Reg Ch1-high
; DMA Stat Reg
; DMA Mode Reg
; DMA/WAIT Control Reg
;System Control Registers
il:
equ
33h
itc:
equ
34h
rcr:
equ
36h
cbr
equ
38h
bbr:
equ
39h
cbar:
equ
3ah
omcr:
equ
3eh
icr:
equ
3fh
; INT Vector Low Reg
; INT/TRAP Cont Reg
; Refresh Cont Reg
; MMU Common Base Reg
; MMU Bank Base Reg
; MMU Common/Bank Area Reg
; Operation Mode Control Reg
; I/O Control Reg
?b
equ
0
?c
equ
1
?d
equ
2
?e
equ
3
?h
equ
4
?l
equ
5
?a
equ
7
??bc
equ
0
??de
equ
1
??hl
equ
2
??sp
equ
3
slp
macro
db
11101101B
db
01110110B
endm
mlt
macro
?r
db
11101101B
db
01001100B+(??&?r AND 3) SHL 4
endm
in0
macro
?r, ?p
out0
otim
6-50
macro
db
db
db
endm
macro
db
?p, ?r
11101101B
00000001B+(?&?r AND 7) SHL 3
?p
11101101B
UM010901-0601