Z85233 Datasheet, PDF (139/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
Interfacing Z80^® CPUs to the Z8500 Peripheral Family
PERIPHERAL INTERRUPT OPERATION
Understanding peripheral interrupt operation requires a
basic knowledge of the Interrupt Pending (IP) and Interrupt
Under Service (IUS) bits in relation to the daisy chain. Both
Z80 and Z8500 peripherals are designed in such a way
that no additional interrupts can be requested during an
Interrupt Acknowledge cycle. This allows that interrupt
daisy chain to settle, and ensures proper response of the
interrupting device.
The IP bit is set in the peripheral when CPU intervention is
required (such conditions as buffer empty, character
available, error detection, or status changes). The
Interrupt Acknowledge cycle does not necessarily reset
the IP bit. This bit is cleared by a software command to the
peripheral, or when the action that generated the interrupt
is completed (i.e., reading a character, writing data,
resetting errors, or changing the status). When the
interrupt has been serviced, other interrupts can occur.
The Z8500 peripherals use /INTACK (Interrupt
Acknowledge) for recognition of an Interrupt Acknowledge
cycle. This pin, used in conjunction with /RD, allows the
Z8500 peripheral to gate its interrupt vector onto the data
bus. An active /RD signal during an Interrupt Acknowledge
cycle performs two functions. First, it allows the highest
priority device requesting an interrupt to place its interrupt
vector on the data bus. Secondly, it sets the IUS bit in the
highest priority device to indicate that the device is
currently under service.
Figure 3. Z8500 Interrupt State Diagram
6-4
UM010901-0601