Z85233 Datasheet, PDF (28/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.2.7 Z80X30 Reset
The Z80X30 has three software resets that are encoded
The Z80X30 may be reset by either a hardware or software
reset. Hardware reset occurs when /AS and /DS are both
Low at the same time, which is normally an illegal condi-
tion. As long as both /AS and /DS are Low, the Z80X30
recognizes the reset condition. However, once this condi-
tion is removed, the reset condition is asserted internally
for an additional four to five PCLK cycles. During this time,
any attempt to access is ignored.
into two command bits in WR9. There are two channel re-
sets, which only affect one channel in the device and
some bits of the write registers. The command forces the
same result as the hardware reset, the Z80X30 stretches
the reset signal an additional four to five PCLK cycles be-
yond the ordinary valid access recovery time. The bits in
WR9 may be written at the same time as the reset com-
mand because these bits are affected only by a hardware
reset. The reset values of the various registers are shown
2
in Table 2-4.
Table 2-4. Z80X30 Register Reset Values
Hardware RESET
WR0
WR1
WR2
WR3
76543210
00000000
00X00X00
XXXXXXXX
XXXXXXX0
WR4
XXXXX1XX
WR5
0XX0 0 0 0X
WR6
XXXXXXXX
WR7
XXXXXXXX
WR7'* 0 0 1 0 0 0 0 0
WR9
1 1 0 0 0 0XX
WR10 0 0 0 0 0 0 0 0
WR11 0 0 0 0 1 0 0 0
WR12 X X X X X X X X
WR13 X X X X X X X X
WR14 X X 1 1 0 0 0 0
WR15 1 1 1 1 1 0 0 0
RR0
X1XXX1 0 0
RR1
RR3
RR10
000
000
0X0
00
00
00
11X
000
000
Notes:
*WR7' is available only on the Z80230.
Channel RESET
76543210
00000000
00X00X00
XXXXXXXX
XXXXXXX0
XXXXX1XX
0XX0 0 0 0X
XXXXXXXX
XXXXXXXX
00100000
XX0XXXXX
0XX0 0 0 0 0
XXXXXXXX
XXXXXXXX
XXXXXXXX
XX1 0 0 0XX
11111000
X1XXX1 0 0
0000011X
00000000
0X000000
UM010901-0601
2-9