Z85233 Datasheet, PDF (77/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Data Communication Modes
4.1 INTRODUCTION (Continued)
For asynchronous data, the Transmit Shift register is for-
matted with start and stop bits along with the data; option-
ally with parity information bit. The formatted character is
shifted out to the transmit multiplexer at the selected clock
rate. WR6 & WR7 are not used in Asynchronous mode.
Synchronous data (except SDLC/HDLC) is shifted to the
CRC generator as well as to the transmit multiplexer.
SDLC/HDLC data is shifted to the CRC Generator and out
through the zero insertion logic (which is disabled while the
flags are being sent). A 0 is inserted in all address, control,
information, and frame check fields following five contigu-
ous 1s in the data stream. The result of the CRC generator
for SDLC data is also routed through the zero insertion log-
ic and then to the transmit multiplexer.
4.1.2 Receive Data Path Description
On the ESCC, the receiver has an 8-byte deep, 8-bit wide
Data FIFO, while the NMOS/CMOS version receiver has a
3-byte deep, 8-bit wide data buffer. In both cases, the Data
buffer is paired with an 8-bit Error FIFO and an 8-bit Shift
Register. The receive data path is shown in Figure 4-2.
This arrangement creates a 8-character buffer, allowing
time for the CPU to service an interrupt or for the DMA to
acquire the bus at the beginning of a block of high-speed
data. It is not necessary to enable the Receive FIFO, since
it is available in all modes of operation. For each data byte
in the Receive FIFO, a byte is loaded into the Error FIFO
to store parity, framing, and other status information. The
Error FIFO is addressed through Read Register 1.
CPU I/O
Internal Data Bus
I/O Data buffer
BRG
Input
Upper Byte (WR13)
Time Constant
Lower Byte (WR12)
Time Constant
16-Bit Down Counter
DIV 2
Status FIFO
10 x 19 Frame*
Rec. Data FIFO** Rec. Error FIFO**
BRG
Output
See
Note
See
Note
See
Note
DPLL
IN
DPLL
Internal TXD
14-Bit Counter
Hunt Mode (BISYNC)
Rec. Error Logic
DPLL
OUT
SYNC Register
& Zero Delete
3-Bit
Receive Shift
Register
RxD
1-Bit
MUX
NRZI Decode
MUX
CRC Delay
Register (8 bits)
SYNC
CRC
To Transmit Section
SDLC-CRC
CRC
Checker
CRC Result
Notes:
* Not with NMOS.
** Rec. Data FIFO and Rec. Error FIFO are 8 Bytes Deep (ESCC), 3 Bytes Deep (NMOS/CMOS).
Figure 4-2. Receive Data Path
4-2
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