Z85233 Datasheet, PDF (298/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Write Register 0 (non-multiplexed bus mode)
D7 D6 _{D5 D4 D3 D2 D1 D0}
0 0 0 Register 0
0 0 1 Register 1
0 1 0 Register 2
0 1 1 Register 3
1 0 0 Register 4
1 0 1 Register 5
1 1 0 Register 6
1 1 1 Register 7
0 0 0 Register 8
0 0 1 Register 9
0 1 0 Register 10
0 1 1 Register 11
1 0 0 Register 12 *
1 0 1 Register 13
1 1 0 Register 14
1 1 1 Register 15
0 0 0 Null Code
0 0 1 _{Point High}
0 1 0 _{Reset Ext/Status Interrupts}
0 1 1 _{Send Abort (SDLC)}
1 0 0 _{Enable Int on Next Rx Character}
1 0 1 Reset Tx Int Pending
1 1 0 _{Error Reset}
1 1 1 _{Reset Highest IUS}
0 0 _{Null Code}
0 1 _{Reset Rx CRC Checker}
1 0 _{Reset Tx CRC Generator}
1 1 _{Reset Tx Underrun/EOM Latch}
* With Point High Command
Figure 1. Write Register 0 Bit Functions
(Non-Multiplexed Bus Mode)
Application Note
Interfacing the ISCC™ to the 68000 and 8086
ster 0 (multiplexed bus mode)
5 D4 D3 D2 D1 D0
0 0 Null Code
0 1 Null Code
1 0 Select Shift Left Mode
1 1 Select Shift Right Mode ^*
0
0 0 0 Null Code
0 0 1 Null Code
0 1 0 Reset Ext/Status Interrupts
0 1 1 Send Abort
0 0 Enable Int on Next Rx Character
0 1 Reset Tx Int Pending
1 0 Error Reset
1 1 Reset Highest IUS
Null Code
Reset Rx CRC Checker
Reset Tx CRC Generator
Reset Tx Underrun/EOM Latch
nnel Only
Figure 2. Write Register 0 Bit Functions
(Multiplexed Bus Mode)
BUS DATA TRANSFERS
All data transfers to and from the ISCC™ are done in bytes
regardless of whether data occupies the lower or upper
byte of the 16-bit bus. Bus transfers as a slave peripheral
are done differently from bus transfers when the ISCC is
the bus master during DMA transactions. The ISCC is
fundamentally an 8-bit peripheral but supports 16-bit
buses in the DMA mode. Slave peripheral and DMA
transactions appear in the next sections.
Data Bus Transfers as a Slave Peripheral
When accessed as a peripheral device (when the ISCC is
not a bus master performing DMA transfers), only 8 bits
transfer. During ISCC register read, the byte data present
on the lower 8 bits of the bus is replicated on the upper 8
bits of the bus. Data is accepted by the ISCC only on the
lower 8 bits of the bus.
ISCC^™ DMA Bus Transfers
During DMA transfers, when the ISCC is bus master, only
byte data transfers occur. However, data transfers to or
from the ISCC on the upper 8 bits of the bus or on the lower
8 bits of the bus. Moreover, odd or even byte transfers
activate on the lower or upper 8 bits of the bus. This is
programmable and explained next.
During DMA transfers to memory from the ISCC, only byte
data transfers occur. Data appears on the lower 8 bits and
replicates on the upper 8 bits of the bus. Thus, the data is
written to an odd or even byte of the system memory by
address decoding and strobe generation.
During DMA transfers to the ISCC from memory, byte data
only transfers. Normally, data appears only on the lower 8
bits of the bus. However, the byte swapping feature
UM010901-0601
6-3