Z85233 Datasheet, PDF (188/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

loop:
chkloop:
ld
bad_data:
good:
enddma:
;
fill_mem: l
fill_loop:
fill_00:
fill_00l:
UM010901-0601
Application Note
The Z180™ Interfaced with the SCC at MHZ
Table 14. Test Program – Z180/SCC DMA Transfer (Continued)
call
initdma
ld
b,0
;init status
7
ld
a,00h
out
(scc_data),a
;load 1st data to be sent
ld
a,11001100b
out0
(dstat),a
;enable dmac and int from DMA0
ld
a,05h
out
(scc_cont),a
ld
a,01101000b
out
(scc_cont),a
;select WR5
;start tx
ei
;wait here for completion
bit
1,b
jr
z,loop
;rx dma end?
;not, then loop again
push
ld
ld
ld
a,(de)
cpi
jr
jp
inc
jr
pop
set
jr
pop
bc
bc,length
de,tx_buff
hl,rx_buff
nz,bad_data
v,good
de
chkloop
bc
2,b
enddma
bc
;save bc reg
;compare tx data with rx data
;restore bc
;set error flag
;restore bc
jr
$
;tx/rx completed
you can put breakpoint here
d
hl,temp
ld
bc,length
ld
de,tx_buff
ld
(hl),00h
ldi
jp
nv,fill_00
dec
hl
inc
(hl)
jr
fill_loop
; prepare data to be sent
; set length
ld
bc,length
ld
de,rx_buff
ld
(hl),00h
ldi
ret
nv
dec
hl
jr
fill_00l
; clear rx buffer area to zero
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